Does this sound more feasible?
15.2.1 Registers(...)The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source onthe T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counteruses to increment (or decrement) its value. The Timer/Counter is inactive when no clock sourceis selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).(...)
16.3 External Clock Source(...)Enabling and disabling of the clock input must be done when T1/T0 has been stable for at leastone system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.Each half period of the external clock applied must be longer than one system clock cycle toensure correct sampling. The external clock must be guaranteed to have less than half the systemclock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector usessampling, the maximum frequency of an external clock it can detect is half the sampling frequency(Nyquist sampling theorem). However, due to variation of the system clock frequencyand duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it isrecommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.(...)