No, I was thinking read from ADC, write 4 bytes to SD. Read, write 4 bytes. Every 128 cycles (512 bytes), close the sector, start another, whatever that process is.
The 2nd ADC I found did dual 16 bit conversions with 4 bytes ready to read every 1uS.
40Kz is 25uS, x2 would be 80KHz, 12.5uS. So just 40 clock cycles at 16MHz.
What if the ADC read is the same set of clock pulses that puts it in the SD so the uC is not buffering the data all, just creating the CS and SCK?
I made a digital delay line for 12-bit audio a ways back, read a parallel 12-bit ADC, wrote it to parallel 16-bit SRAM (4 bits not used), had user selected delay time to read it back and write to 12-bit DAC. Output mixed in analog to feed into input for repeats. Had 3 delays so multiple delay times could be mixed in (remember Australian group "Men At Work"? Someone told me they used multiple echos for their sound, was going for something like that). Worked well. I still have, big board of parts all wirewrapped up.