Help Change timer 2 to timer 0

Ok it now compiles! However, I now get this error when attempting to load the sketch onto the attiny85:

avrdude: please define PAGEL and BS2 signals in the configuration file for part ATtiny85
avrdude: please define PAGEL and BS2 signals in the configuration file for part ATtiny85
avrdude: verification error, first mismatch at byte 0x03d3
         0xd1 != 0xff
avrdude: verification error; content mismatch