Phase shifting PWM outputs is entirely possible. You can even get high resolution phase control, especially when generating low frequencies. I also think the PWM engine with its complementary pairs is best suited and probably required for this type of application.
Its possible to use just one sine data array, then the index you use for each signal will determine the phase shift. I've experimented with the PWM engine and was able to get 0.01 degree phase control resolution for a specific 3-phase power application. The sine data array only needs to be one quadrant (90 deg) in order to create the full cycle of required data points. The rate of incrementing the index determines the filtered sine output frequency. For 3 PWM output pairs (A,B,C) shifted by 120 degrees, the index values would be i, i+12000, i+24000.
Another application requirement might have 1 degree phase control using one array with 360 data points.
In this case, the index values would be i, i+120, i+240. Care needs to be taken to never read past the array size and to cycle back when i+shift >359.
Anyone interested in using the PWM engine (PWMH/PWML), this is the code I used to initialize the PWM and clock but it would need to be customized/cleaned up to suit your own application:
//Configure PWM channels 0,1,2,3 (PWML0,PWMH0,PWML1,PWMH1,PWML2,PWMH2,PWML3,PWMH3), (port C.2,C.3,C.4,C.5,C.6,C.7,C.8,C.9), (pins P34,P35,P36,P37,P38,P39,P40,P41)
REG_PIOC_PDR = 0x3FC; //B1111111100, PIO Disable Register
REG_PIOC_ABSR = REG_PIOC_ABSR | 0x3FCu; //B1111111100, Peripheral AB Select Register
REG_PMC_PCER1 = REG_PMC_PCER1 | 16; //Peripheral Clock Enable Register 1 (activate clock for PWM, id36, bit5 of PMC_PCSR1)
REG_PWM_ENA = REG_PWM_SR | B1111; //PWM Enable Register | PWM Status Register (activate channels 0,1,2,3)
REG_PWM_CMR0 = 0x10000; //Channel Mode Register: Dead Time Enable DTE=1
REG_PWM_CMR1 = 0x10000; //Channel Mode Register: Dead Time Enable DTE=1
REG_PWM_CMR2 = 0x10000; //Channel Mode Register: Dead Time Enable DTE=1
REG_PWM_CMR3 = 0x10000; //Channel Mode Register: Dead Time Enable DTE=1
REG_PWM_DT0 = 0xA800A8; //PWM Channel Dead Time Register (168=2us for outputs PWML0,PWMH0)
REG_PWM_DT1 = 0xA800A8; //PWM Channel Dead Time Register (168=2us for outputs PWML1,PWMH1)
REG_PWM_DT2 = 0xA800A8; //PWM Channel Dead Time Register (168=2us for outputs PWML2,PWMH2)
REG_PWM_DT3 = 0xA800A8; //PWM Channel Dead Time Register (168=2us for outputs PWML3,PWMH3)
REG_PWM_CPRD0 = 5600; //1/5600 resolution for VoltsA (84mhz/5600=15khz=66.667us period)
REG_PWM_CPRD1 = 5600; //1/5600 resolution for VoltsB (84mhz/5600=15khz=66.667us period)
REG_PWM_CPRD2 = 65535; //16 bit resolution for VoltsA DC Power Supply amplitude (84mhz/65535=1.281khz=780.64us period)
REG_PWM_CPRD3 = 65535; //16 bit resolution for VoltsB DC Power Supply amplitude (84mhz/65535=1.281khz=780.64us period)
//configure sine clock
REG_PMC_PCER0 = REG_PMC_PCER0 | 0x80000000; //Peripheral Clock Enable Register 1 (activate clock for TC4, id31, bit31` of PMC_PCSR0)
TC_Configure(/* clock */TC1,/* channel */1, TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_TCCLKS_TIMER_CLOCK3); //TIMER_CLOCK3 = MCK/32 = 2,625,000 Hz