Was just reviewing the watchdog timer in the datasheet for the ATmega328P, and while it's nominally advertised as having a 128KHz clock, from the chart below it seems that the design point is around 10% slower than that. Might this represent some sort of safety factor to allow slightly "late" watchdog resets to squeak through?
The accuracy of the 8MHz RC oscillator is rated as +/-10%. If the same applies to the Watchdog oscillator, then it might be that the design frequency is chosen so that the real frequency never (or rarely) exceeds 128kHz.