Looks like the ATTiny25/45/85 hardware will support SPI:
Port B, Bit 2 – SCK/ADC1/T0/USCK/SCL/INT0/PCINT2
• SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as
a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDPB2. When the pin is
forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.
Port B, Bit 1 – MISO/AIN1/OC0B/OC1A/DO/PCINT1
• MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as
a Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI
is enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is
forced by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.
Port B, Bit 0 – MOSI/AIN0/OC0A/OC1A/DI/SDA/AREF/PCINT0
• MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as
a Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is
forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.