What datarate are you sampling at?
CD quality audio is sampled at 44.1K samples/second.
You could probably get by with 32K samples at 12Bit sampling.
For "a few seconds" you will need "a few" banks of 32k x 8 SRAMs with 2 SRAMs in each bank.
That will support an audio frequency range of ~15KHz.
You'll have to do the math and see if you can use Serial interface RAM (SPI), or parallel.
Parallel would need 15 address lines, 12 data lines, WE/,OE/ to all chips and a CE/ to each bank.
If coding supports direct port manipulation, then you might have something like:
sample time?{
read adc
write high address port with output address
write low address port with output address
write data port
write control line port for CEx low
write control line port for CEx high
update output address count & CEx if needed
write high address port with input address
write low address port with input address
write control line port for CEx low
read data port
write control line port for CEx high
write DAC
update input address count & CEx if needed
}
the delta in address range between the write address and the read address (which must be lower than the write address) will determine the delay.
You'll have to take care to wrap the address counter back around to 0 after reaching the last address of the last bank and to ensure that the read address always follows the write address.