Accessing DUE usart status registers..

Hi. I have a rs485 module connected to my due and I have problems.. ermh.. while transmitting over rs485.. Yes.. The same old problem; I need to put RTS pin high while transmitting and set it low again to receive.. Problem is that RTS pin is closed too early so the data being sent.. Isn't complete.

2 solutions:

  1. add a delay. This works.. And then again it doesn't. Length of delay should be dependant on the data that was sent. As we don't know the buffer in all cases, all it varies.. This isn't good. Ofcourse, we could add a delay long enough.. But then receiving might fail, because other end might already be answering to the query..

  2. use status registers of usart to detect if transmission buffer is empty/transmission has ended/or something else.. Here's a popular atmega code:

while (!(UCSR0A & (1 << UDRE0)))  // Wait for empty transmit buffer
     UCSR0A |= 1 << TXC0;  // mark transmission not complete
 while (!(UCSR0A & (1 << TXC0)));   // Wait for the transmission to complete

Well this nonsense doesn't work on the due.. Here's something that I've been trying:

  while (USART1->US_TCR == 0 );
  while ((USART1->US_IER & US_IER_ENDTX ) != US_IER_ENDTX );
  while ((USART1->US_CSR & US_CSR_ENDTX ) != US_CSR_ENDTX );
  while ((USART1->US_IER & US_IER_TXBUFE ) != US_IER_TXBUFE );
  while ((USART1->US_CSR & US_CSR_TXBUFE ) != US_CSR_TXBUFE );

Neither of those lines did the trick or anything towards the solution.. I am using Serial1, so I guest USART1 is correct, right?
Little help needed here :slight_smile:

jake1981:
I am using Serial1, so I guest USART1 is correct, right?

Serial1 is USART0. Take a look at the Due Pinout Diagram thread at the top of the forum.

Ouch! That's true :slight_smile: tx0 and rx0.. Should had figured that out..

Okay, not a really concern for me atleast on moment.. But what about Serial output? And SerialUSB?

Although, changing to USART0 did nothing :confused:

Use the flush() method of HardwareSerial object to wait until the transmission is completed.

just for completeness, this is how the flush is implemented:

void USARTClass::flush( void )
{
  // Wait for transmission to complete
  while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
	yield();
}

Thanks.