Sorry, I was thinking about schematics like this: Driving P-Channel MOSFETs with a Microcontroller
No worries, I thought something was up....
Perhaps I've misinterpreted the app note entirely, so let's start from basics.
VGG is not a connection from another device such as an NPN transistor, but it's simply the power supply ground? Your wording seems to imply VGG is controlled by another device not pictured.
Figure 3 that uses an N MOSFET on the high side, I think I understand - as of course - when the circuit is powered up, VDD = 12V (for arguments sake) and so the gate is charged through CGD' and RGD, slowly - which prevents inrush.
Is that correct? Further, I didn't think you should/could ever use NMOS on the high side?
Only when we've sorted these issues, then let's move onto the PMOS application of Figure 1 
Cheers!