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Topic: Can spi MOSI pin be idle low ? (Read 2098 times) previous topic - next topic

yang_changwei

When SPI enabled.

The MOSI pin seems to be idle high,
even I send a 0x00 through MOSI, it returns to HIGH.

is there anyway to make it low?

MorganS

"The problem is in the code you didn't post."

yang_changwei

Hi MorganS,

Thanks, but I am referring the MOSI pin, not the CLK pin.

When SPI peripheral takes over the MOSI pin,
it seems it let it park at High level which I want it to be low.

dlloyd

It seems to be part of the SPI protocol for MOSI, MISO and SS (or CS) to be normally high. Why do you need idle low?


CrossRoads

You should not even be looking at MOSI anyway if your slave Select is not active.

SCK High or Low can be determined by the SPI Mode you are running:
https://www.arduino.cc/en/Reference/SPI
Designing & building electrical circuits for over 25 years.  Screw Shield for Mega/Due/Uno,  Bobuino with ATMega1284P, & other '328P & '1284P creations & offerings at  my website.

Ratskrad

Has this question been answered - the only option I see is to add an external gate or FET to invert MOSI to allow idle low. This seems to be a limitation of AVR only as ARM based arduino allow MOSI to idle low.

The reason to do this is that some synchronous serial peripherals require MOSI low before /CS otherwise they ignore sent data.

Mark.

ard_newbie

#6
Jan 23, 2018, 07:29 am Last Edit: Jan 23, 2018, 07:30 am by ard_newbie
There is a known issue with the MISO line with some SPI devices, but MOSI should not be an issue:

https://www.dorkbotpdx.org/blog/paul/better_spi_bus_design_in_3_steps

However, due to the full-duplex nature of the SPI driver, for every byte sent on the MOSI line, a byte is received on the MISO line. So if you send 5 bytes and want to read one byte, in response, you need to read 5 bytes and consider the 5th byte as the real "response" from the slave.

Ratskrad

#7
Jan 23, 2018, 07:57 pm Last Edit: Jan 23, 2018, 08:14 pm by Ratskrad
Thanks for your reply. It looks like I will have to add an external gate to hold MOSI low until SS is asserted. Here is the peripheral datasheet (NCV7719) - I am using 5 devices in a daisy chain.





ard_newbie

#8
Jan 23, 2018, 08:40 pm Last Edit: Jan 23, 2018, 08:40 pm by ard_newbie
Seems that some SPI interfaces behave strangely.

Instead of adding hardware, you can reconfigure the MOSI line in GPIO output and set it to low via software. Once done, the MOSI line can be reconfigured as a peripheral line handled by the SPI peripheral ?.

Ratskrad

Interesting idea. I tried driving the line high as an output before sending words, but as soon as SPI is configured (SPE in SPCR) it controls the line and overrides the GPIO function.

I also tried sending 0x00 before my data to force MOSI low, but it defaults back to high when /SS deasserts.

As you suggest- I'll see if I can configure MOSI as a GPIO output and output low before engaging SPI mode and see if that will allow it to idle low (maybe the pull-ups are still enabled).

Mark

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