Note that this device has a 195A continuous rating. The avalanche rating is the current/time window you must keep within when conduction is caused by over-voltage breakdown, i.e. avalanche, it is NOT the safe operating area of the device in normal operation. If your circuit and layout is carefully designed (basically no parasitic inductance between the drain and any clamping diode), the FET may never avalanche at all!
Vishay AN1005 (pdf) explains it nicely.
If you're going to design against the avalanche guidelines (necessary if you're pushing up against the device's voltage limits), you just need to make sure that the worst-case current pulse though the FET due to reverse breakdown of the body diode fits within the avalanche SOA.
Since this project has 12V on tap and the FET is rated for 40V, it's not in much danger at all unless the design and/or PCB layout are truly horrible. Certainly you don't need to keep the PWM pulses under 100us!