This is what Don (a customer) said in an email regarding the same issue:
I did look at the clocking relationships on the scope.
The clock to data hold timing on the HC164 was marginal, 2ns, versus -2ns typical and 4ns minimum. Meaning it will probably work, but it's not certain. CLK, DATA and WR are buffered through 2 sections of an HC04, with a delay of 11ns, but CS_OUT is not, so with every successive board in a chain this timing degrades. They ran out of HC04 gates. Installing the 10pf capacitor at C1 might help, but it's not ideal.