Looks like the problem with reads at 42 MHz only occurs if the data buffer for the read is in the top 32 KB of memory.
SRAM for the SAM3X is two banks, SRAM0 - 64 KB, and SRAM1 - 32 KB. The stack is at the top of SRAM1 so when the interrupt for sysTick happens, registers are pushed on the stack in SRAM1. This blocks access to SRAM1 by the DMA controller and I get an SPI overrun error. If I disable interrupts during the 512 byte DMA transfer, no error occurs. Too bad the SPI controller doesn't have a FIFO. At 42 MHz, the SPI bus delivers a byte about every 200 ns.
It takes about 100 usec for a 512 byte transfer so it's too long to disable interrupts.
Most people will have their buffers in the first 64 KB of SRAM0 and access to to this bank works fine with 42 MHz SPI. Also SPI at 28 MHz works with buffers in SRAM1.
DMA at 28 MHz is still fast:
Type is FAT16
File size 40MB
Buffer size 61440 bytes
Starting write test. Please wait up to a minute
Write 2834.49 KB/sec
Maximum latency: 90293 usec, Minimum Latency: 20612 usec, Avg Latency: 21666 usecStarting read test. Please wait up to a minute
Read 3056.74 KB/sec
Maximum latency: 20401 usec, Minimum Latency: 19993 usec, Avg Latency: 20098 usec
The sending of 0XFF bytes to drive SPI clock have nothing to do with the problem.