ShiftPWM SPI Clock signal noise

pylon:
On this picture Digital 0 is the clock signal and Bus is the data signal? What's the sample rate of your USBee? More than 10MS/s? Doesn't look that bad to me. From the speed I'd guess you're using the hardware SPI, aren't you?

Can you define "noise problems"? How do these show up?

Both signals are clock, one is "analog" reading the other is digital. Usbee runs at 16mbps.

YouTube this is how it looks like. There should be one triangle lit up at one time.

And yes its hardware SPI that ShiftPWM uses on Mega its 52,51 and 8 for latch