Brilliant, thanks - I'm with you both on all accounts. I'm not actually using the Arduino IDE for this project, so it's just co incidence that I'm using the 2560 chip in the design - I had looked at using a number of the smaller chips that supported external memory, but by the time I'd added external ADCs and port expanders / multiplexers to get my required I/O, a much bigger chip was cheaper and simpler.
The datasheet says "Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM." (not including any wait-states that are configured.) It's not entirely obvious whether that's because of the multiplexing, or for some other reason.
If its one cycle per byte, and not per bit - that would say to me that's the latch signal as that is the only additional step it is taking as compared to internal SRAM is it not?