Composite Video Generating

This is just the DMA section of the code:

// Continuous DMA -> SMC port (pins 34-41)
// by stimmer

// set up 2 DMA buffers and a linked list
// 888 and 222 is NTSC timings (~15750 buffers/sec)
uint8_t dmabuf[2][888];
uint32_t dmall[10]={(uint32_t)dmabuf[0],0x60000000,0x22060000+222,0x20000000,(uint32_t)(dmall+5),
                    (uint32_t)dmabuf[1],0x60000000,0x22060000+222,0x20000000,(uint32_t)dmall};
int cbuf=0; // current buffer index

void  DMAC_Handler()
{ 
    uint32_t dummy=REG_DMAC_EBCISR; // clear DMA interrupt flag
    dmall[2+5*cbuf]=0x22060000+222; // may not be needed

  // write to dmabuf[cbuf] here   
  // you only have 6 clock cycles per byte!  
  // write words and longs where you can for speed
  
    cbuf=1-cbuf;
}

void setup() {
  
  // set up memory controller
  REG_PMC_PCER0= 1<<9; 
  REG_SMC_SETUP0=0;  
  REG_PIOC_PDR=0b1111111100;
  REG_PIOC_ABSR&=~0b1111111100;  
  REG_SMC_WPCR=0x534d4300;
  REG_SMC_SETUP0=0x00000000;
  REG_SMC_PULSE0=0X00000101;
  REG_SMC_CYCLE0=0X00000006; // this sets the DMA rate -  84/6=14 MByte/sec
  REG_SMC_TIMINGS0=0;
  REG_SMC_MODE0=0x00000000;
  
  // this code puts DMA priority above CPU.
  MATRIX->MATRIX_WPMR=0x4d415400;
  for(int i=0;i<6;i++)MATRIX->MATRIX_MCFG[i]=1;
  MATRIX->MATRIX_MCFG[4]=4;
  for(int i=0;i<8;i++)MATRIX->MATRIX_SCFG[i]=0x01000008;
  MATRIX->MATRIX_SCFG[6]=0x011200ff;
  MATRIX->MATRIX_PRAS0=MATRIX->MATRIX_PRAS1=MATRIX->MATRIX_PRAS2=0x00000000;
  MATRIX->MATRIX_PRAS3=MATRIX->MATRIX_PRAS4=MATRIX->MATRIX_PRAS5=0x00000000;
  MATRIX->MATRIX_PRAS6=0x00030000;
  MATRIX->MATRIX_PRAS7=MATRIX->MATRIX_PRAS8=0x00000000;

  // set up DMA
  REG_PMC_PCER1= 1<<7;  
  REG_DMAC_WPMR=DMAC_WPMR_WPKEY(0x444d4143);
  REG_DMAC_EN=1;
  REG_DMAC_GCFG=0x00;
  REG_DMAC_CFG5=0x10702200;
  REG_DMAC_DSCR5=(uint32_t)dmall;
  REG_DMAC_EBCIER=1<<5;
  NVIC_EnableIRQ(DMAC_IRQn);
  
  // start DMA
  REG_DMAC_CHER=1<<5;

}

void loop() {
  
}