Go Down

Topic: Maximum number of shift registers cascading (TPIC6B595) (Read 1 time) previous topic - next topic

houile

Hi everyone!

I need to control many outputs (332 to be specific) so i have put 42 shift registers TPIC6B595 cascading.
But only the first 24 are working. After that, i get nothing.

I tried to send a wrong number of bytes but it behave exactly the same way, as if all the bytes above 24 were discarted. If i send less, it does not work properly, as i expected.

Does anybody know if there is a limitation to the number of TPIC6B595 you can cascade? I didn't find this information on the datasheet or any topic her.

Thanks for your help !

PaulRB

It's not a limitation of the tpic chip. The problem is probably the clock and latch lines. They go in parallel to every chip, and have to go over a much longer distances of wire.

You could try some buffer chips. Many basic 7400 series logic chips can be used, such as 7400, 7404 etc. After the 16th shift register, buffer the clock & latch lines. Same after the 32nd shift register. The data line should be ok because that gets buffered by each shift register.

Additional Note (suggested by Paul_S): "7400" logic series were invented back in the 1960's. Since then, newer replacements have been developed using newer technologies. The chips we buy today are usually the "LS" or "HC" versions, so for example the 74LS00 or the 74HC04. Either will be fine for your circuit. Buy whatever's cheaper.

Also, you must have a 1.0uF bypass cap for each chip, near the 5V & ground pins. Depending on what the chips are driving, and how fast switching is happening, lots of smoothing caps is also a good idea.

Something to test: could the 24th or 25th tpic chip be faulty? Try swapping some chips around.

houile

Hello Paul and thanks for your help.
I've been trying to figure out what the issue is these past few days but now i am realy stuck.

I've put a 74HCT04 after the 12th chip and the 28th chip. By testing them, i found out i had a low level (around 2,5V) on the output of the 2nd buffer chip, on my LATCH wire. This was due to a very tiny short circuit between LATCH and GND around my 36th chip.

After fixing this issue, this is the behaviour i have :
- from chip 1 to 12, everything works fine
- from chip 13 to 28 (betwenn the two 74HCT04) the signal is one pin ahead : if i try to power pin 7 from chip 12, it will power it AND pin 0 from chip 13. When i try to power pin 0 from chip 13, it will power chip 1, etc.
- from chip 29 to 32, the signal is 1 AND 2 pins ahead. If i try to power pin 0, it will power pins 1 and 2.
- from chip 33, it doesn't respond and stays on (but weak because of too much power consumption) all the time.

I made many tests but can't figure what is wrong. The buffer chips seem to put an offset so i will try to run the DATA wire thru the buffer too, so if there is a delay it will be the same. My soldering might also be at fault!

Do you have any other suggestion?

PaulRB

Please explain the problems again. But this time use the names of the tpic chip pins, not the pin numbers. Nobody memorises pin numbers because life is too short. Also explain what you mean by "the signal is one pin ahead" and "if i try to power pin 7 from chip 12, it will power it AND pin 0 from chip 13". You should power the chip through the pin called Vcc and no other pin.

You did not answer my questions about bypass caps, or swapping chips.

A schematic would be very helpful. You don't need to show every tpic chip,  just show chips 1, 2, 11, 12, 27, 28, 36 and the buffer chips.

houile

Thanks again for your help. Sorry, i did not mean pin numbers, but drain number.

My problem now is when i send datas in order to open drain x, it opens drain x+1 instead. When a try to open last drain (n°7) of a TPIC chip, if opens drain 0 from next TPIC chip.

Depending on if i use one, two or zero 74HCT04 chip, the issue starts from a different TPIC chip. I will try to draw a schematic but it is quite large et and made a lot of changes for testing purpose.

About the bypass caps, do you think it may be the source of the issue? Everything is soldered on custom made PCB (i know, maybe i went too fast!) so it's not easy to add that much caps on them. Do you think one cap per group of 4 chips could be ok?

I have tried to swap chips, but so far it did not make any difference.

Grumpy_Mike

Quote
About the bypass caps, do you think it may be the source of the issue?
Yes along with the lack of buffering for the clock and latch pins.

Quote
so it's not easy to add that much caps on them
Yes it is. If you add surface mount ceramic caps to the pins on the underside of the board you can put one on each chip, which is the recommended number.

Quote
Also, you must have a 1.0uF bypass cap for each chip,
I would use 0.1uF ceramic capacitors.


houile

Well i get the lack of buffering may be a problem, but i had new issues when i put the buffer chips so now i am trying to figure out what is causing the problem because it looks like there are several sources.

What i am doing right now is removing all the TPIC chips and puting them back one by one to understant at what point the problem starts.

I will buy some more caps and follow your advice, but you say 0,1uF and Paul says 1,0uF so i don't realy know which to buy. I'll ask google :)


Grumpy_Mike

Quote
but you say 0,1uF and Paul says 1,0uF so i don't realy know which to buy.
Yes Paul made a typo.

Quote
What i am doing right now is removing all the TPIC chips and puting them back one by one to understant at what point the problem starts.
What will happen is that the more you add the more unreliable it will be. You might see it working in the short term but continued testing will show occasional errors. It is not worth doing any plugging in tests until you have the decoupling capacitors and the buffers sorted out.

PaulRB

I would use 0.1uF ceramic capacitors.
Oops, typo, sorry, I meant 0.1uF not 1.0uF! Thanks Mike.

PaulRB

My problem now is when i send datas in order to open drain x, it opens drain x+1 instead. When a try to open last drain (n°7) of a TPIC chip, if opens drain 0 from next TPIC chip.

Depending on if i use one, two or zero 74HCT04 chip, the issue starts from a different TPIC chip. I will try to draw a schematic but it is quite large et and made a lot of changes for testing purpose
74hc04 are inverting buffers, so you should use them in pairs on the same line. If you use just one, the clock and latch signal will be inverted and strange things will happen. Use two together and the signal is buffered but not inverted.

houile

Thanks again for your help. Maybe if i had read the entire datasheet i would have known about these evil capacitors !

You are not the only one making mistakes PaulRB : i asked for 0.1uF capacitors at the store, and they gave me 0.01uf capacitors! Fortunately i realised that... just after soldering all of the 43 capacitors.

But even with the wrong value, it works well almost always. I still need to run some more tests but if i notice occasional errors i will just replace them.

About the 74HC04, i use them in pairs. My debug might have been messed up by other errors, but i'm pretty sure these buffers apply a tiny delay, so i made the DATA wire go through it too so they stay in sync.

PaulRB

Quote
i'm pretty sure these buffers apply a tiny delay
Absolutely true. But that delay is insignificant compared to the delay caused to the data line by passing through a dozen shift register chips!

Grumpy_Mike

#12
Oct 09, 2017, 10:21 pm Last Edit: Oct 09, 2017, 10:22 pm by Grumpy_Mike
Quote
i would have known about these evil capacitors
No No.
It is not the capacitors that are evil, they are your friends, they combat the evil.

You did ask for ceramic capacitors did you? Is that what you got?

CrossRoads

#13
Oct 09, 2017, 10:34 pm Last Edit: Oct 09, 2017, 10:34 pm by CrossRoads
What size (gage) wire are you using for +5 and Gnd? If it's too small, you may have dips on the supply line and voltage surges on the Gnd line as the TPIC outputs turn on and pull the pins low.
How many buffer chips do you have? I daisychained 45 TPIC6B595, with a buffer chip for the signals for every 9 chips.
Designing & building electrical circuits for over 25 years.  Screw Shield for Mega/Due/Uno,  Bobuino with ATMega1284P, & other '328P & '1284P creations & offerings at  my website.

houile

Thank you for your messages. This made me mad so i stopped for a few days :)

But that delay is insignificant compared to the delay caused to the data line by passing through a dozen shift register chips!
Possible. So the delay is not relevant, as it is designed to chain chips with DATA passing througth and CLOCK not passing througt ? I should not worry about it at all?

It is not the capacitors that are evil, they are your friends, they combat the evil.
I know. But if they are required it is evil that they are not built in.
I have ceramic capacitors now, but reading old messages made me realise i forgot they are not the ones required and i still need to change those !

What size (gage) wire are you using for +5 and Gnd?
I distribute power with 0,2mm² wires to every PCB holding 4 chips.


The more i try, the less this is working. A few days ago i only had some bugs, now the entire thing is a mess. What i changed, to be in real conditions, is i use longer wires to cary infos from the arduino to the chips (about 2-3 meters).
I've put buffers before the first chip, but it's still not working : random lights are on, and they blink realy fast when i try to send datas.
Maybe the issue with long wires is reflections, so i think maybe low pass filters would help on CLOCK and DATA. I think the datasheet says DATA is a 5kHz signal but i am not sure.

Also i have noticed some voltage variation on my circuit. Would it be better with 3 separate power supply for the light bulbs, the chips, and the arduino ? Now i have a 30A 5,5V power supply which is the best option to power everything, but not the best to power each part.

I will probably give it a last shot if you guys have any suggestion, but i am starting to realize i started something way too hard for me !


Go Up