I am trying to measure resistance with analog input. The only difference is I am not using an external voltage divider. I am trying to use the internal pullup resistor to form a voltage divider with the external resistor.
I know that the internal pullup is not very accurately quoted, maybe up to 40Kohm.
I know that enabling the internal pullup means a transistor is turned on thus a voltage drop will reduce the effective voltage of the divider to something less than 5V, maybe 4.6V.
I am trying to measure this voltage drop V_DS, or the rest of the voltage, V_eff, and the pullup resistor R_int.
Here is what I did, I connected R1=10Kohm resistor between A0 and GND and measured V1=1.119V.
I then connected R2=40Kohm resistor between A0 and GND and measured V22.584V.
I suspect V_ref=5.05V from USB power supply.
The resistors are 1%.
Then I solved the voltage divider equations and found the following:
V1/Veff=R1/(R1+R_int)
V2/Veff=R2/(R2+R_int)
V_int.=30.9Kohm
V_eff.=4.58V
I wonder if these numbers are right or not. My calculations based on these numbers seem a bit off from measurements with different resistors, by a few percent.
You are under a misapprension - the internal "pull-up resistors" on the chip are probably FETs with a long thin channel that behaves roughly like a high value resistance, but won't be very linear. To fab an actual resistor on silicon takes a lot more chip real estate than a FET, and is only done when necessary such as in analog opamps.
There is a single transistor current limiter that is Very predictable and compliant when used at 1 to 5 % of it's collector current. I'd use that circuit for a programmable current generator and measure the voltage across the test resistor generated by this CC gen with the internal 1.1 Vrf. It sounds complicated but it is a couple of transistors or gates to shift the CC gen output range or a DAC to program the CC gen. The circuit will work with the minimum to the max where the A/D Vref is gated or a DAC under program control establishes a known current then measures the voltage to determine the unknown 'resistance'. The point is that this can magnify the basic 10 bit res by quite a bit without so very much complicated or arcane op-amp things. Really interestiing things even with limited pin count applications.
MarkT:
You are under a misapprension - the internal "pull-up resistors" on the chip are probably FETs with a long thin channel that behaves roughly like a high value resistance, but won't be very linear. To fab an actual resistor on silicon takes a lot more chip real estate than a FET, and is only done when necessary such as in analog opamps.
Probably true, since there needs to be an FET to turn on the "pullup resistor" in the first place. All diagrams I read on doc8237 are functional diagrams instead of the actual circuits I suppose. But here is some reference (doc8237) that might answer my question:
I wonder what Vop represents. This diagram is for Vcc=5V so if I understand Vop as voltage applied to the IO pin that is in input state and has pullup enabled, then it tells me there is no voltage drop for the FET and the equivalent resistance is about 35.7Kohm, judging from the slope. Can someone with more understanding of this diagram give me some hint? Thanks.
Docedison:
There is a single transistor current limiter that is Very predictable and compliant when used at 1 to 5 % of it's collector current. I'd use that circuit for a programmable current generator and measure the voltage across the test resistor generated by this CC gen with the internal 1.1 Vrf. It sounds complicated but it is a couple of transistors or gates to shift the CC gen output range or a DAC to program the CC gen. The circuit will work with the minimum to the max where the A/D Vref is gated or a DAC under program control establishes a known current then measures the voltage to determine the unknown 'resistance'. The point is that this can magnify the basic 10 bit res by quite a bit without so very much complicated or arcane op-amp things. Really interestiing things even with limited pin count applications.
Bob
Bob, I am coming up short, not having enough analog circuit experience
Well looking at that graph the internal 'pull-up' look pretty linear to me. I think what you want to determine is what is the output impedance of a digital input pin when it's internal pull-up is enabled. So looking at the graph I would look at the current value when the pin is at 1/2 Vcc or 2.5vdc and it would seem that it is about 70ua. So R= 2.5/70ua = 35.7 kohms, which should represent the output impedance rating for the pin.
As the spec is nominal and subject to tolerances, you might want to run an actual test on your specific pin. Wire a say 100k pot, one end and the wiper from pin to ground and decrease resistance until pin voltage is equal to one half Vcc, then remove the pot and measure it's resistance and that should be equal to the output impedance of that input pin when the intenal pull-up is enabled.
