hi,
kein problem, du mußt dann nur das:
LD __tmp_reg__, %a[dataptr]+" "\n"
" LSL __tmp_reg__" "\n"
" LDI %[bits], 4" "\n"
" BRCC L13" "\n"
" RJMP L5" "\n"
" H1: NOP" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" NOP" "\n"
" RJMP END" "\n"
" L1: SUBI %[bits], 1" "\n"
" BREQ M2" "\n"
" NOP" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" LSL __tmp_reg__" "\n"
" OUT %[portout], %[upreg]" "\n"
" BRCC L8" "\n"
" NOP" "\n"
" L15: NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" RJMP L9" "\n"
" M4: LDI %[bits], 4" "\n"
" LD __tmp_reg__, %a[dataptr]+" "\n"
" OUT %[portout], %[upreg]" "\n"
" NOP" "\n"
" NOP" "\n"
" SUBI %[bytes], 1" "\n"
" BREQ H1" "\n"
" LSL __tmp_reg__" "\n"
" BRCS L9" "\n"
" NOP" "\n"
" L16: OUT %[portout], %[downreg]" "\n"
" NOP" "\n"
" L13: OUT %[portout], %[upreg]" "\n"
" LSL __tmp_reg__" "\n"
" OUT %[portout], %[downreg]" "\n"
" BRCC L10" "\n"
" SUBI %[bits], 1" "\n"
" BREQ M4" "\n"
" NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" LSL __tmp_reg__" "\n"
" OUT %[portout], %[upreg]" "\n"
" BRCS L15" "\n"
" NOP" "\n"
" L8: NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" RJMP L16" "\n"
" M2: LDI %[bits], 4" "\n"
" OUT %[portout], %[downreg]" "\n"
" NOP" "\n"
" OUT %[portout], %[upreg]" "\n"
" LD __tmp_reg__, %a[dataptr]+" "\n"
" SUBI %[bytes], 1" "\n"
" BREQ H1" "\n"
" LSL __tmp_reg__" "\n"
" BRCC L16" "\n"
" NOP" "\n"
" L9: OUT %[portout], %[downreg]" "\n"
" NOP" "\n"
" L5: OUT %[portout], %[upreg]" "\n"
" LSL __tmp_reg__" "\n"
" BRCS L1" "\n"
" SUBI %[bits], 1" "\n"
" BREQ M1" "\n"
" NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" LSL __tmp_reg__" "\n"
" OUT %[portout], %[upreg]" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" BRCC L4" "\n"
" NOP" "\n"
" L12: NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" RJMP L5" "\n"
" M3: LD __tmp_reg__, %a[dataptr]+" "\n"
" OUT %[portout], %[upreg]" "\n"
" LDI %[bits], 4" "\n"
" OUT %[portout], %[downreg]" "\n"
" SUBI %[bytes], 1" "\n"
" BREQ H2" "\n"
" LSL __tmp_reg__" "\n"
" BRCC L16" "\n"
" NOP" "\n"
" RJMP L5" "\n"
" L10: SUBI %[bits], 1" "\n"
" BREQ M3" "\n"
" NOP" "\n"
" NOP" "\n"
" LSL __tmp_reg__" "\n"
" OUT %[portout], %[upreg]" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" BRCS L12" "\n"
" NOP" "\n"
" L4: NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" RJMP L13" "\n"
" M1: LD __tmp_reg__, %a[dataptr]+" "\n"
" OUT %[portout], %[downreg]" "\n"
" LDI %[bits], 4" "\n"
" OUT %[portout], %[upreg]" "\n"
" NOP" "\n"
" OUT %[portout], %[downreg]" "\n"
" SUBI %[bytes], 1" "\n"
" BREQ H2" "\n"
" LSL __tmp_reg__" "\n"
" BRCS L9" "\n"
" NOP" "\n"
" RJMP L13" "\n"
" H2: NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" NOP" "\n"
" END: NOP" "\n"
so umschreiben, daß es zur taktfrequenz des DUE paßt, und dann natürlich auch noch an die anzahl der verwendeten strips anpassen.
was ich damit sagen will:
das ist KEINE sache, die Du mit einem sketch lösen kannst, und Du wirst hier im (deutschsprachigen) forum niemanden finden, der das kann. nimm Dir zwei UNOs, lass die beiden miteinander reden und zwei streifen steuern. einer davon ist der "master". dann nimm den anderen, den "slave", aus dem UNO raus, steckst ihn auf ein breadboard, und einen neuen ATMega328 mit bootloader um 3€ in den sockel des uno. dann kannst Du drei miteinander reden lassen. wenn Du dann, sagen wir mal, fünf hast, bist Du fertig. fünf chips, die zusammen 2400 rgbLEDs steuern können. anders wirst Du das nicht lösen können.
gruß stefan