So why the complex timing arrangement with two timed interrupts keeping the processor busy all the time?
Not really sure about the "interrupts keeping the processor busy all the time" part. Interrupts are useful precisely because they do not keep the processor busy - they interrupt the processor only when certain conditions are met.
And, most importantly, if the timing part underestimates the load that driving the DAC will have on the program, ...
I do not know how the DAC part is to be implemented. The DAC could be really fast - a parallel DAC for example, or it could be preloaded by the main loop and strobed / activated by the isr. It could be implemented without causing excessive delays in the isr, rendering your question moot.
First, test the DAC, ...
Different ways of skinning the cat. Without knowing all the details, it is impossible to assert if one approach is better than another.