Coding Badly is right, the only way to insure low noise due to ADC sample time jitter is to auto trigger the ADC with Timer/Counter1 Compare Match B.
At the rate chaveiro is sampling, 1600 samples per second, sub microsecond jitter is needed to avoid jitter noise in the AVR 10 bit ADC. The jitter SNR must be greater than 62 dB to get 10 bit ADC accuracy.
The formula for ADC jitter noise is
SNR = 20log(1/(2pift))
where f is the sample frequency and t is the jitter time.
with 0.1 usec jitter the SNR is about 60, just about good enough.
SNR = 20log10(1/(6.281600*1e-7)) = 59.96
Here is a calculator for ADC jitter Design Tools & Calculators | Design Center | Analog Devices
It gives 9.71e-8 seconds max jitter for full accuracy of a 10-bit ADC at 1600 samples per second.