the shift registers are driven with hardware SPI @ fosc/2. it turned out that this is not the limiting factor. most of the time is burned to do the PWM in the ISR routine.
(spi)-->SR1-----------SR2----------------SR3------------SR4
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row red column green blue
select cath. 0-7 cath. 0-7 cath. 0-7
(anodes)
that's all. no transistor arrays yet. SR1 might be supported by an UDN2981A in the future for more current output for each of the row pins. what's also possible is to move the row selection to arduino pins for more speed using direct port manipulation.