The next generation of the Propeller chip is currently under development by Parallax. Nothing is certain about this chip so far, but Parallax has told the community about a lot of features they are expecting to included 8 COGs, 128K Hub RAM (tentatively Beau Schwabe has said 256K is still a possibility), 128 KB ROM, 92 I/Os, and 160Mhz.
Early on they had talked about going with 16 COGs, but due to silicon size and other considerations they have gone back to 8. This may change, or they might do another version later with 16.
In order to have 128 KB RAM and 128KB ROM, they had to expand. They decided to go all the way to 32bit.
ADC/DAC "EVERY one of the 92 pins will have one these babies in it, along with a comparator, a delta-sigma ADC, a delta-sigma DAC, a high speed signal/video 75-ohm DAC, pull-ups/downs, slew control, float/weak/strong HIGH/LOW combos, schmitt input w/feedback, crystal oscillator, and a few other things"
The only downside that it runs at 1.8v
And here is the Propeller 2 Preliminary Feature List.
General:
- 32-bit, general purpose multi-core microcontroller
- 8 identical processors (cogs)
- Planned 128-pin SMT package(1)
Clock Speed:
- 160 MHz planned maximum clock speed(1)
- Internal RC: 20 kHz or 20 MHz (cannot use PLL)
- External oscillator: DC to 160 MHz (without PLL) or 10 MHz to 32 MHz (with PLL) for system clock speed of 160 MHz maximum(1)
- PLL modes: 2x, 4x, 8x, 16x input clock multiplier
Performance Metrics:
- 4-stage pipeline
- Most instructions are single cycle
- 1.28 BIPS (160 MIPS x 8 cogs) maximum instruction execution rate(1); assumes that all cogs are running, their pipelines are always full, and only single-cycle instructions are being executed
Memory:
- Main memory: 128 KB RAM(2) + 32 KB ROM planned
- Cog memory: 2 KB (512 longs) cog RAM
- Optional external 32-bit addressable SDRAM for run-time data workspace; code space is not extendable
- Non-volatile application and data storage via external SPI EEPROM or SD card
- Cogs can access Main Memory at each hub access window in units of 1 byte, 1 word, 1 long, or 4 contiguous quad-aligned longs.
- Hub access window arrives for each cog in a round-robin fashion every 8 cycles.
Power Specifications:
- Core voltage: 1.8 VDC
- I/O pin voltage: 1.8 VDC–3.3 VDC
- Current source or sink per I/O: 40 mA
- Total current draw @ 1.8 VDC Core, 3.3 VDC I/O, 25° C: TBD
I/O:
- 92 I/O pins total: 84 fully general purpose I/O + 8 additional general purpose I/O available after boot-up
- Each I/O pin is planned(1) to have internal:
o Input ADC
o Output DAC
o True or inverted input/output
o Differential input/output
o Comparator
o Schmitt input
Counter Modules:
- 2 counter modules, each with 2 integrated waveform generators, per cog
Math:
- Hardware multiplier and divider
- Hardware CORDIC system
Video Generation:
- Each cog has independent video generation hardware capable of VGA, Standard PAL/NTSC, and HD up to 1080p (at 30 Hz).
Code Protection and Encryption:
- Propeller application and data optionally encrypted in non-volatile storage
Supported Languages:
- Propeller 2 Spin and Propeller 2 Assembly
- Propeller 2 Assembly is not fully backwards compatible with Propeller 1 Assembly
- Some Propeller 1 Spin code may need to be ported to the Propeller 2
*And all I/Os can be used for SPI and I2C.
I also learned today that each cog can be used as a UART. So that is 8 UARTs Cool
1.28 BIPS, All I can say is wow.
