After re-reading the document I posted above (about the level shifter) I think I understand it better. But as I read it, it is for I2C and not SPI. In particular this sentence:
The devices of each section have I/Os with supply voltage related logic input levels and an open-drain output configuration.
But SPI is not open-drain (whereas I2C is). This may not matter. But the technical note specifically mentions I2C (and even mentions SDA and SCL), so there may be some subtle "gotcha" when trying to use it for SPI. For example, a timing issue.