Nested interrupt handlers, anyone?
That is one fundamental difference, by default on the Due you are not safe from other interrupts when in an ISR.
how to emulate something as conceptually simple as "cli" an a processor like the ARM,
I've done this on an LPC
#define ATOMIC_START __disable_irq();__interruptLevel++;
#define ATOMIC_END if ((__interruptLevel) && !(--__interruptLevel))__enable_irq();
I haven't tested it yet and may have a -- in the wrong place or something but the idea is that I disable all interrupts at the start of an atomic block but only re-enable them if they were enabled when I entered the block.
Rob