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Topic: Resetting Due QDEC counter register (Read 356 times) previous topic - next topic

marcdavidson

I'm having some issues resetting the TC0_CV0 register when using the quadrature decoder module on the Due.
This register should be reset when the SWTRG bit in the TC0_CCR register is set. I do this by disabling the clock with REG_TC0_CCR0 = 2;
This disables the clock and
then restarting it with
REG_TC0_CCR0 = 5;
The counter does get reset but not right away. And it seems somewhat unpredictableI'd like to have more control of this register  than what I'm currently getting.
Waiting for the counter to reset after restarting using, for instance
while(TC0_CV0);
doesn't work either. It sits there forever.
Any help would be appreciated.


ard_newbie


marcdavidson

When cleaning up my code before posting it, I must have removed the problem. In any case the attached code works.
Thanks


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