Cortex M0+ variants - what is common ??

Well, the SWD protocol is standard, and there's a USB-level protocols that's standard (CMSIS/DAP), and a supposedly flexible OSSW program for doing stuff (OPENOCD), so in theory there are a bunch of devices (EDBG, mEDBG, nEDBGm ST-LINK, Segger, LPCXpresso, TI Launchpad, and so on and on) that do approximately the same thing, and ought to be able to program chips from multiple vendors.

In reality, each chip has it's own flash programming algorithm, and with <$100 solutions from each vendor that work "seamlessly" with their chips, there's not a lot of motivation for writing those algorithms at the openocde level and making things "generic" (the "NVM Controller", in charge of writing to flash - that's one of the vendor-specific peripherals.)

The closest thing to "generic" is probably the ST-Link/V2 Example Cheap Version
See for example Adalink for software to use it, and a framework for defining new CPUs.