A couple of points.
- who commented out the delays in the I2C driver?
- you need to ignore the SYNC line at this point. It makes no sense to read it until you have followed the setup procedure for the chip.
- you are not understanding the datasheet correctly. The master only ever sends an ACK when it is READING. In this case it is writing.
- I started to analyse your traces until I noticed someone had tampered with the driver. The clock seems to be doing the right thing but the SDA appears to be random (which is no wonder if someone has f*cked up the timing)
Anyway...I'm not inviting a barrage of unrelated questions but attached is a trace from a LA which shows EXACTLY what the trace should look like with NO ack from the slave.
and also the first write to a different address to show you what the ACK pulse timing should look like.
HTH.