I use fibreoptic endoscopes for work, and have just got hold of an older Pentax 'scope for filthy cheap money, as it just needed a few minor repairs but didn't come with a light source.

~150W is the typical power level for halogen light sources for this purpose, but I can deal with less.

I have a fibre optic xmas tree and it uses one of these to focus light into the bundle through a colour wheel. Not as powerful as you wanted but maybe a cluster of them would do the job.

Do you actually focus the light into the fibre bundle, or just point the lamp at the end? My fibre connector has a 3mm diameter opening for light, hence thinking I need a little focus. Just wondering if a high power LED would do the job.

Something like this, driven with a 12V source.

Hi all,

I'm looking at building up a light source for a bunch of fibre optic cable - I need about 100-150W in terms of typical halogen bulb power...

However, I'm not sure about how to focus this light into a fibre optic bunch - some have mentioned torch lenses etc, but will that not simply melt the end of the fibre bunch? Or perhaps a magnifying glass, that focuses the light onto a mirror, which reflects the light into the source - that way, should a large amount of the heat be dissipated in the mirror?

Any ideas / suggestions appreciated.

Cheers

Hi all,

I've been working on a board for nearing 6 months now, that will ultimately be embedded away and hard to get to for me - but, I'd still like the option of having the ISP & JTAG lines accesible over a cable with cable distances of roughly 2 meters.

What are the likely challenges / issues with this? Seems JTAG themselves recommended very short cables http://www.jtagtest.com/faq/jtag-ieee-1149-1/how-long-should-the-jtag-cable-be

I've heard something about increasing the signal strength using a buffer, but I can't say I'm entirely sure I know what that means?

Cheers

Thanks for all your replies, that's certainly answered!

Hi all,

I'm adding USB connectivity in a design I'm working on, but don't wish to provide 5V from the USB port/cable itself as I've got 5v and 3v3 regulated on the board from a 12V supply.

However, do I still need to connect the ground pin from the USB port/cable to the boards ground?

Cheers!

I'll be switching both static and/or PWM depending... The chips recommended look like a nice little device, however - a little help reading the datasheet(s) if possible - how does one know if a device is suitable for static switching, or PWM only?

Hi all,

I've got some high side p-channel MOSFETs providing high side general purpose power switches from a board I'm working on, but as mentioned to me in a thread - you can of course use NMOS if you've got a high enough voltage available for the gate relative to source (why it took somebody to tell me this as opposed to me seeing it is besides the point )

Can anybody a) recommend a high sided NMOS gate driver, as the obvious ones such as the MAX1614 seem to be aimed at power distribution applications in devices such as phones etc, and so have multiple pins for other purposes I don't need.

and b) or alternatively, can I not just use a DC-DC converter to give me the voltage I need (appropriately sized for switching current of course) to drive NMOS gates on the high side?

Using N-channel on high side would be possible if a voltage for the gate is available that is higher than the source or the drain. Like I wrote, that is almost never the case.

That I don't have, so that removes that possibility.

As for the PMOS application, yes - let's hope some others can chime in here too...

Cheers!

Sorry, I was thinking about schematics like this: http://circuit-zone.com/index.php?electronic_project=438

No worries, I thought something was up....

Perhaps I've misinterpreted the app note entirely, so let's start from basics.

V_GG is not a connection from another device such as an NPN transistor, but it's simply the power supply ground? Your wording seems to imply V_GG is controlled by another device not pictured.

Figure 3 that uses an N MOSFET on the high side, I think I understand - as of course - when the circuit is powered up, V_DD = 12V (for arguments sake) and so the gate is charged through C_GD' and R_GD, slowly - which prevents inrush.

Is that correct? Further, I didn't think you should/could ever use NMOS on the high side?

Only when we've sorted these issues, then let's move onto the PMOS application of Figure 1 

Cheers!

When I say defeats the point entirely, I am referring to the fact that the circuits presented are there to switch the load on slowly, whilst Figure 1 does not seem to do this.

So yes, we're talking about Figure 1, for sure.

For example with a resistor from Gate to Source to keep the Gate at 12V.
If the Load is switched on slowly, the Gate should be slowly lowered from 12V to a lower voltage. Perhaps with a NPN-transistor with its collector to the Gate.

Figure 1 does not have a gate-source resistor, nor any NPN transistor for this purpose.

R_GD and C_GD' are there to provide the slow ramp of gate voltage - like I said in my original post, I understand how these passives are doing exactly that in Figure 3, but not in Figure 1. As Figure 1 defaults to on, i.e. does not prevent inrush current, hence - defeats the point, as the point is to prevent inrush current.

Thanks for your reply.

In Figure 1, the 12V is the Source pin of the P-channel MOSFET.
If the Gate is low, the P-channel MOSFET is switched on.
If the Drain is 12V, the Load is powered. But the Gate is still low and the Source is still 12V, keeping it switched on.
To slowly switch the load on, the Gate voltage has to be lowered slowly from 12V to a lower voltage.
Does that answer your question ?

I'm afraid not, no - the whole purpose of the solutions proposed in the app note are to ramp the MOSFETs on slowly so as to prevent high inrush currents.

If as you say, the gate is at 0 volts (because it's connected to the 0v rail), and you apply power to the circuit, i.e the source becomes 12V - then V_GS is -12V, and the MOSFET is switched fully on, which then allows a large inrush current to flow immediately.

Hence, defeats the point entirely.

[However, a question - I thought one should never use NMOS in a high side application, only ever in the ground return?]

Hi all,

So - to prolong the life of all the caps on a design I'm working on, and to prevent tripping of anything, I've been looking at inrush protection using MOSFETs. Now, Motorola have a nice app note, AN1542 about this exact issue. http://www.bonavolta.ch/hobby/files/MotorolaAN1542.pdf

However, there's a couple of little caveats that I don't quite understand.

Figure 3 on page 8 uses an NMOS FET to control inrush current by charging the gate slowly, i.e. limiting how fast gate voltage rises. Of course, with N FETs, V_GS must be positive for the device to turn on. So the schematic makes sense.

However, a question - I thought one should never use NMOS in a high side application, only ever in the ground return?

Figure 1 however, also on page 8, uses PMOS to do the same job. However - I can't figure it out, P FETs require V_GS to be negative for the device to turn on. So, question - when you first apply power to the circuit, the source is say 12V, and the gate is at 0V, so V_GS is negative - and the FET is switched fully on, defeating the point entirely?

Am I wrong?

[potentially]

I'm using the suppressors to deal with flyback when switching inductive loads, as per my other thread you've helped in - hence the power dissipation.

The MOSFETs have an on resistance of only a few mOhms, and are only switching ~5A at the 10s of kHz.

The IGBTs are driving inductive loads, at currents of ~10A up to around 75Hz. The h-bridge is a VNH2SP30, so no - no bipolars here thankfully! Stepper chip uses MOSFETs in the bridges too.

The problem will arise in the future I foresee, with up to 20 high side switches potentially, so this thread was more to get a feel to see if the solution was viable re cooling.

Cheers!

BTW you can get power mosfets that are rated at greater than 5mJ repetitive avalanche energy, so your tranzorb is theoretically redundant if you use one of those. But including the tranzorb is kinder to the mosfet.

I had looked at these yes, but decided to stick with a transient suppression diode. Thanks for your input!

Thanks for the replies...

I still think the first priority should be to see if the power consumption of the circuit can be reduced.

This is of course my first priority, at the moment I'm not dissipating anywhere near that power - but a future version will include the possibility for multiple high side, high current power switches which will up the dissipation.

(...just because I've just done the calculation...) as an example, on the board are 8 transient suppressors dissipating up to ~400mW each, so we're at 3.2W.

Now include the 12V regulator, 5V regulator, 3.3V regulator, 8 MOSFETs driving not insignificant currents, 4 IGBTs that are self clamping, h-bridge IC, stepper motor IC all tightly packed into a 100 x 80mm double sided PCB.

When I get a moment at some point today, I'll do a full calculation of the worst case power dissipation and report back.