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Has anybody similar experiences with the tiny's max ISP speed?
I do. There is some variance (I assume because of different fabs / batches). With some processors I have had success programming over the recommend SPI bitrate but never by more than double. I have never had problems using 125 KHz SCK for targets running at 1 MHz and 2 M SCK for targets running at 8 MHz.
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(I could have mis interpreted the data sheet).
My interpretation is not the same. This is from the t85 datasheet...
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Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
That is greater than 2 CPU clock cycles for CPU clock speeds less than 12 MHz.
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I see no way to configure the Due for a slower SPI.
Use bit-banging. Nick Gammon has an implementation on his site that can probably be dropped-in.
