The problem that you are having results from settings in the CTRL1 and CTRL4 registers.
There's an ap note (AN3308) on the ST site. here's a link that might workhttp://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/CD00290365.pdf?s_searchtype=keyword
You have to set the Lpen and HR bits correctly after you start up the chip by setting the ODR bits.
Lpen is in the CTRL1 register and HR is in the CTRL4 register.
It seems there are only two legit settings for these bits
1 0 Low Power Mode
0 1 Normal Mode
any other settings of these bits will cause the output to glitch. It looks like, when incorrectly set, only one of each data register is filled.
The ApNote has some other juicy bits in it that I'm just digging into...
Hope that helps