So if edge detectors are not used, explain clock recovery. What does edge mean in the spec when it says the card will do this on leading edge or that on trailing edge. Where are these edges on your plot of the signal.
I am not saying edge detectors are not used - I showed how an "edge detector" could look like..
Clock recovery needs some "edges" - but they must not come in a regular periodic manner (as you know from SPI clock for example) as you can use X-methods to recover a "regular periodic" clock from a data stream where the clock is not directly "visible" (used everywhere today). The data stream is created in a manner it contains the clock inside it - all communication works in that manner today..
So you have to distinguish between "to detect the edges physically - rise/fall of a signal" and "to detect the edges logically - like the clock in Manchester coding"..
Could you point me to the spec you mention, plz?
What plot of signal of mine do you mean? Do you mean the edge detectors above? I can imagine a clock recovery could be possible when we generate the clock (those 600MHz for the flip-flops clocking) with an VCO which is (phase) locked to the pulses from the edge detectors above. The recovered clock appears as the variation of the voltage at the pll low pass filter. That is how it works when you have bit streams which contain clock info. But that is not "heavy DSP" - it is a simple loop with some analog stuff around.
PS: maybe you point on the Single Data Rate and Double Data Rate signalling:
• SDR12 - SDR up to 25MHz 1.8V signaling
• SDR25 - SDR up to 50MHz 1.8V signaling
• SDR50 - SDR up to 100MHz 1.8V signaling
• SDR104 - SDR up to 208MHz 1.8V signaling
• DDR50 - DDR up to 50MHz 1.8V signaling
I've seen 800mA current spec - so I have to change my guessing on the sdcard controller speed inside - that could be easily: an 32bitter @1GHz