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Author Topic: how do I minimize ADC clock freq via a register?  (Read 626 times)
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I see from the data sheet of the micro controller that ADPS2-0 affect this, but I am not sure how in code to do this.

I'll continue to scour the forums but your help is appreciated

Thanks
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The ADPSn bits are part of the ADCSRA register. You can set them using code like the following -

Code:
// ADC clock prescaler 8
ADCSRA |= (1 << ADPS1) | (1 << ADPS0);

That's untested but it should work. The exact combination of bits that you turn on affects the pre scaler, but you know that already from reading the data sheet smiley

Look up bit wise operations/bitmath for more information about what is going on, or search for something like "AVR set bit"
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The ADPSn bits are part of the ADCSRA register. You can set them using code like the following -

Code:
// ADC clock prescaler 8
ADCSRA |= (1 << ADPS1) | (1 << ADPS0);

That's untested but it should work. The exact combination of bits that you turn on affects the pre scaler, but you know that already from reading the data sheet smiley

Look up bit wise operations/bitmath for more information about what is going on, or search for something like "AVR set bit"


Thanks!
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Other than the prescaler for the ADC, is there another register I can write to so that I can slow the ADC clock even more? 

Thanks
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Why do you want to  slow it? That will make the conversion time longer, and may affect the accuracy of the sample & hold circuit that is charged up prior to making the conversion.
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Why do you want to  slow it? That will make the conversion time longer, and may affect the accuracy of the sample & hold circuit that is charged up prior to making the conversion.

I need to perform DSP on an audio signal and want the bins to have a small frequency span for better granularity.  This is for a spectrum analyzer display.
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