You can get out-of-phase signals from the same timer if you put it in one of its PWM modes and configure the TCCRxA register for toggling on compare match.
For example, let's take Timer 1 (Section 16.11 of the ATmega328P datasheet). Configure it for CTC mode 12 (WGM1[3:0]=0b1100) so that the ICR1 register defines the TOP timer value, hence the frequency (PWM frequency will be 16 MHz/(ICR1+1)). Then, configure the TCCR1A register so that OC1A and OC1B both toggle on a compare match.
Now set OCR1A=ICR1-1, OCR1B=OCR1A/2. This means that once every timer period (from TCNT1=0 to TCNT1=ICR1) there will be a compare match with OCR1A and it will toggle, and approximately half a period later there will be a compare match with OCR1B and it will toggle.
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