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[on:]

Im using the 74LS08 quad AND gate, in a simple circuit connecting it to a dip switches, but it doesnt seem to work, do i need pull up or pull down resistors and why?

[Reply #1 on:]

do i need pull up or pull down resistors and why?

The dip switch is just an open/close switch, but the signal needs to be HIGH/LOW, not HIGH/undefined
So yes, you need a pulldown, if the swich supplies HIGH when on.

Any unused input pin of an AND gate has to be high, too.
Alternatively, you can supply a signal to more than one pin.

[Reply #2 on:]

thankyou, but what i dont understand is that if i dont connect my inputs to anything the gate takes that as a HIGH. so i have just connected the dip switch to ground without any resister and it is working fine.

[Reply #3 on:]

from http://www.kpsec.freeuk.com/components/74series.htm regarding 74LS...

Inputs 'float' high to logic 1 if unconnected, but do not rely on this in a permanent (soldered) circuit because the inputs may pick up electrical noise. 1mA must be drawn out to hold inputs at logic 0. In a permanent circuit it is wise to connect any unused inputs to +Vs to ensure good immunity to noise.

For the 74HC.. series ( less power requirements in amount and regulation, slower ) pulling inputs is more important, I agree.

[Reply #4 on:]

can someone please help me to connect a 74LS08 quad and gate to a dip switch? I cant seem to understand how the pull up or pull down resistors work. i want the inputs to go to low when the switch is off and high when the switch is on.

[Reply #5 on:]

What kind of switch? Momentary On push button that is normally open?
3-pin toggle switch with normally open, common, normally closed pins?

[Reply #6 on:]

its a dip switch like this one:

[Reply #7 on:]

This: http://en.wikipedia.org/wiki/AND_gate and this: http://en.wikipedia.org/wiki/Pull-up_resistor are good articles and should answer your question.

[Reply #8 on:]

Lets assume that "Switch on" = switch is in the closed position (pins connected to each other).

In that case, you need a pulldown resistor from the pin to ground, one side of the switch connected to a pin, and the other side connected to +5V.
When the switch is on, the pin is connected to +5, and when the switch is off the pin is pulled low.

[Reply #9 on:]

The 74LS series are TTL - they need pullups of around 1k or so on inputs to guarantee reading high and you MUST NOT connect inputs directly to 5V...
To pull down you need a hard pull-down (ie use a 1k pull-up to 5V and the switch to ground, not the other way round).

Also you have to use pull-ups on a TTL output when its driving a CMOS chip like the ATmega to guarantee that an output HIGH will be seen as HIGH (it will probably work most of the time without, but it is not guaranteed I believe).  TTL levels are not symmetric.

74HC series are the modern CMOS pin-for-pin equivalent, and pullups and pulldowns of 10k to 100k will work fine - avoid TTL if you can, its more expensive as well as slower, power-hungry and difficult to interface to.

[Reply #10 on:]

Please don't start two threads within a few hours of each other about AND gates. Just let the answers flow in from the helpful people here.

Threads merged.

[Reply #11 on:]

can someone please help me to connect a 74LS08 quad and gate to a dip switch? I cant seem to understand how the pull up or pull down resistors work. i want the inputs to go to low when the switch is off and high when the switch is on.

That's not easily doable with TTL as I've mentioned - ideally use push-to-break rather than push-to-make switches, or else feed the switches through inverters.

The problem is that TTL inputs are not really rated for connecting to +5V except through a resistor - the breakdown voltage of the input transistor is only 5.5V (bit close for comfort).   The good news is that I've done a bit more research and the LS series of TTL is more robust in this respect, so you should be able to get away with it - the input transistors can handle upto 7V

You will need a pull-down resistor as low as about 680 ohms though, to pull the inputs properly low, 1k might be a bit too large.

[ and the standard caveat - 0.1uF ceramic decoupling capacitor for every logic chip ]