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Author Topic: Unexplained I2C "spikes" or "glitches"  (Read 1389 times)
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Hi all,

I'm trying to get two arduinos talking to each other via I2C.  The issue is that I get very repeatable "spikes" or "glitches" on my SDA line which happen to line up exactly with the clock's leading edge.  However, these "spikes" are not present the entire time - well, at least at that level....  (Take a look at the attachment for a trace)  Anybody know what might be causing this?

Suffice to say, these little buggers are causing for poor communications....

Mark


* test3.jpg (32.37 KB, 320x234 - viewed 126 times.)
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Are you using external pull-up resistors or relying on the internal?

Read through the following page and you'll probably use external pull-ups.

http://www.dsscircuits.com/articles/effects-of-varying-i2c-pull-up-resistors.html
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Yes, that's an excellent article by Wayne - I've learned quite a bit from his post/s.

Taking off my external 3.2K pullups does make my waveforms uglier (per Wayne's post), but they do nothing to effect (literally no effect) these spikes as shown on the attachment.  Are you suggesting that pullups *should* affect these spikes?  If so, I'd love to learn more about why or how that would be as I'm still learning the ins and outs of this protocol.

Thanks!
« Last Edit: June 05, 2012, 11:18:53 am by mwilkie » Logged

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I'm seeing the same spikes (me only in a rising edge of an expected signal) using a simple pseudo-SPI protocol on my cheap pocket DSO. I always thought of them being measurement errors of the scope. I never had problems with them so I didn't investigate them anymore. I never saw the standalone spikes though.

Are you connecting the Arduinos using a breadboard? Maybe the capacity of it is enough to produce such spikes?
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Yea, I am also mostly concerned with the stand-alone spikes on the sda line which line up timing wise with the rising edge of the clock signal.

To your point, I was wondering about capacitance as well.  There is a breadboard in the loop - however, I took it out and ran one arduino directly to the other just to see if there was a change is these "spikes".  There was none....no change between the two setups.  Does anyone know if too much capacitance would cause this behavior?
« Last Edit: June 05, 2012, 11:20:03 am by mwilkie » Logged

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To follow up, I found the following link which probably explains what I'm seeing.  http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/186350.aspx

Based on the above link, I now suspect I'm seeing the bus being released at the end of a cycle - which is legal so long as scl is low.  So....it's probably software.  (grin)
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