Yes, you can do that, and it is probably better self-documenting. However the code generated is exactly the same. My code:
ISR(TIMER1_COMPA_vect) // timer compare interrupt service routine
100: 1f 92 push r1
102: 0f 92 push r0
104: 0f b6 in r0, 0x3f ; 63
106: 0f 92 push r0
108: 11 24 eor r1, r1
{
if (PINB & _BV (4))
10a: 1c 9b sbis 0x03, 4 ; 3
10c: 02 c0 rjmp .+4 ; 0x112 <__vector_11+0x12>
PORTB &= ~_BV (4);
10e: 2c 98 cbi 0x05, 4 ; 5
110: 01 c0 rjmp .+2 ; 0x114 <__vector_11+0x14>
else
PORTB |= _BV (4);
112: 2c 9a sbi 0x05, 4 ; 5
}
114: 0f 90 pop r0
116: 0f be out 0x3f, r0 ; 63
118: 0f 90 pop r0
11a: 1f 90 pop r1
11c: 18 95 reti
Changing the ISR to read:
ISR(TIMER1_COMPA_vect) // timer compare interrupt service routine
{
if (bitRead (PINB, 4))
bitClear (PORTB, 4);
else
bitSet (PORTB, 4);
}
Gives:
ISR(TIMER1_COMPA_vect) // timer compare interrupt service routine
100: 1f 92 push r1
102: 0f 92 push r0
104: 0f b6 in r0, 0x3f ; 63
106: 0f 92 push r0
108: 11 24 eor r1, r1
{
if (bitRead (PINB, 4))
10a: 1c 9b sbis 0x03, 4 ; 3
10c: 02 c0 rjmp .+4 ; 0x112 <__vector_11+0x12>
bitClear (PORTB, 4);
10e: 2c 98 cbi 0x05, 4 ; 5
110: 01 c0 rjmp .+2 ; 0x114 <__vector_11+0x14>
else
bitSet (PORTB, 4);
112: 2c 9a sbi 0x05, 4 ; 5
}
114: 0f 90 pop r0
116: 0f be out 0x3f, r0 ; 63
118: 0f 90 pop r0
11a: 1f 90 pop r1
11c: 18 95 reti
Every single byte of machine code the same. So it runs at the same speed, to the nanonsecond.
I like it for the better documentation, but don't think it will save time.