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Author Topic: PDI programming - what do these diagonal lines mean?  (Read 789 times)
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I've been trying to write a PDI programmer with moderate success. That is, smoke is not actually emerging from the part. smiley-wink

I'm wondering what is the meaning of the diagonal hatched box (circled) here ...



According to the datasheet (XMEGA A MANUAL Preliminary):

Quote
ST - Store data to PDIBUS Data Space using indirect addressing

The ST instruction is used to store data that is serially shifted into the physical layer shift-register to locations within the PDIBUS Data Space. The ST instruction is based on indirect addressing (pointer access), which means that the address must be stored into the Pointer register prior to the data access. Indirect addressing can be combined with pointer increment. In addition to write data to the PDIBUS Data Space, the Pointer register can be written by the ST instruction. Even though the protocol is based on byte-wise communication, the ST instruction supports multiple- bytes address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). It should be noted that multiple-bytes access is internally broken down to repeated single-byte accesses. The main advantage with the multiple-bytes access is that it gives a way to reduce the protocol overhead.

Well, fair enough, it sounds like the "Size A/B" (RH two bits) might be both the address and the pointer (somehow), but then they give an example:

Quote
Write a value to a address with *(ptr++) instruction through the PDI Controller

Pseudo Directive: ST *(ptr++) 0xFF

PDIBUS hex code: 0x67 0xFF

Now the instruction was 1100 0111

So the "data size" was 4 bytes. But the example only stores one byte!

I can't quite get my head around the example, compared to what the other stuff says. Do they mean, it stores one byte but the pointer advances four? What use is that?
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FIrst thought was was it looks like a spare in bowling..

interpreting the graphics I would say there can either be the size of A 00 01 10 11 or B in there which is explained in the last column (there the same colors are used

so you have a pointer and you know it is pointing to something of 1,2,3,4 bytes so the ++ operator knows how much to "jump"

does this match reality?

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The only reality I have so far is that the device is not getting hot.

I can sort-of see that you might put 0,1,2,3 in that field to indicate you are planning to store 1,2,3,4 bytes (and increment the pointer accordingly) but it seems odd to me to have a 3 there (indicating 4 bytes) but only send a single byte.
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My suspicion is that the example is wrong.  The graphic and the description match each other and make sense.

I would expect four data bytes to follow the opcode and the pointer to be incremented by four *before* the write.
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My interpretation would be light grey for size A and dark grey for size B (Using the same instruction) - a little redundant as both use the same mask, possibly an update in the protocol?
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I guess it is just to display that the command can be fed both addresses (light grey) and data (dark grey), depending on how PTR is set up.
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Ah yes, nice thought. Still it doesn't match the example.

The only possible objection is: what is a 1-byte pointer? I suppose it might imply that the other 3 bytes are zero, and it saves sending those zeroes.
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