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« on: June 10, 2012, 12:34:34 am » |
Okay, I fixed some of my other Eagle symbol problems (got the TL1220 pins to connect, had to use CTRL-click-click to get back on grid), (still not seeing names on the board tho.)
Made a new symbol today for a Vertical USB Mini-B connector, which I think looks great. When I went to use it, I got a totally new Eagle error:
Layer Abuse!
Seems to be a problem with the pads I made to hold the side tabs. Any thoughts on how to fix that?
Thanks!
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What a host of balls she had seen: gaity, the brass buttons...
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« Reply #1 on: June 10, 2012, 08:18:42 am » |
Damn, and there was I thinking "Ultimate Eagle challenge!" would be more like "Fly to Mordor and drop the ring down the top of Mount Doom."
Bah.
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« Reply #2 on: June 10, 2012, 08:43:35 am » |
@majenko, LOL
@CrossRoads, I didn't have any trouble with it. Using Eagle 6.1.0. I added one in to a circuit I was working on, just made a couple connections to it, auto-routed the board, all seems well.
EDIT: Opps, just kidding ... Lots of "Layer Abuse" in the DRC. Hmm.
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« Last Edit: June 10, 2012, 08:45:40 am by Jack Christensen »
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« Reply #3 on: June 10, 2012, 08:49:59 am » |
Jack, You didn't get any errors when you ran the DRC on it? Eagle says its layer 17, Layer Abuse, I am concerned about not having pads to solder to as the autorouter seemed to ignore the error and run traces thru the pad area. You think maybe its an Eagle 6.0 thing?
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« Reply #4 on: June 10, 2012, 09:18:17 am » |
No, my bad, have duplicated the issue  Totally ignorant of custom pads and slots, but it'd sure be nice to know how to do it. See the last comment on this page, a few clues there but I'm still a bit out of context. http://www.element14.com/community/message/47644
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« Reply #5 on: June 10, 2012, 09:49:23 am » |
Thanks Jack, I'll revisit my pad shape and see if can fix it. I see now I need to define more stuff for it.
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« Reply #6 on: June 10, 2012, 10:28:04 am » |
I tried making a new package, used wires to draw the large pads on the top and bottom layers. Then I got overlap errors in DRC. Let me know if you figure this out!
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« Reply #7 on: June 10, 2012, 11:54:07 am » |
@CR, see attached, do you think it might work? I added a second package and corresponding device variant to the library. I used polygons for top and bottom layer "pads" and just a wire segment of the proper width on the milling layer for the slot. Also put a "real" pad right in the middle, this could be used to make connections or could just be deleted. SMD pads might be better. Used rectangles for tStop and bStop. I'd want to check with the board house to see if this would work. A separate Gerber file would probably be needed for the milling layer, and verify that the through-hole metallization happens after the slots are milled. I sure couldn't find much information out there regarding how to do this. Here is another link: http://www.eaglecentral.ca/forums/index.php?t=msg&th=6530&start=0&bbc6a99c47700643dae9addf80173a55/
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« Reply #8 on: June 10, 2012, 12:39:01 pm » |
I don't think that quite does it. There is no hole visible, and the autorouter is willing to put a trace thru the pad. Which the DRC then calls an overlap error.
When I did my attempt, I made the oval with 20Dimension and then added the lines around it to make the pad. Maybe I need to take those lines and call them something else.
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« Last Edit: June 10, 2012, 12:42:16 pm by CrossRoads »
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I only ever use XAND and XNAND gates.
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« Reply #9 on: June 10, 2012, 01:08:25 pm » |
I found this forum thread and after reading it real quick, it looks like it says that when you have non-pads/vias in the pads/vias layer.
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« Reply #10 on: June 10, 2012, 01:17:14 pm » |
I think I have a solution. I changed the 17Pads lines to 1Top and copied them to 16Bottom. Looks like this now. Hole from the 20Dimension oval seems to show up on the Gerbers, the autorouter keeps traces out of the pads, and DRC does not complain anymore. Think I need a Symbol box around it to show mechanical outline and to see when the device is mirrored like I am using it.
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