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Author Topic: MOSFET vs. transistor  (Read 1588 times)
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Shannon Member
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From the datasheet the output transistors (they are FETs, not gates) on-resistance is about 40 ohms with a 5V supply about 60 ohms with a 3V supply. That's about 65mW and 90mW dissipated in the output transistor at the abs max current of 40mA (at 5V and 3V respectively.  That's a lot of power for one CMOS FET (it'll be quite a large FET compared to most on the die of course, but it'll still be microscopic), and exceeding the current limit will cause thermal stress, or thermal damage, or in extreme localised melting of the chip and interconnect.

If the manufacturer says the abs max limit is 40mA, stick to that limit if you want reliable operation (unless you are prepared to run your own series of long-term reliability tests to further characterise the chip's response to current pulses!)

If you short an output pin at 5V it will likely dissipate 600mW in the output transistor (10 times abs max), probably raising its temperature at something like a few thousand deg C per second - that _rate_ of heating will cause mechanical stress even if only for a few milliseconds - mechanical stress can lead to failure too.
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I think you misunderstood me I stated several reasons why it wasn't a good idea to max out a Proc pin and they are gates. 2 totem pole transistors one, the top one a P-Ch fet with a modified gate drive for biasing on the weak input pull-ups and the second the N-Ch fet to pull down the output as the top is switched off to allow the the lower one to pull down the output just an inverted drive from - to the top P-Ch fet gate.

Doc
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You mean the kind of gate made from two complementary FETs that carry the current?

A gate is an abstraction that processes logic values, a transistor carries current.  If talking about the current/voltage/resistance/etc, you hop down an abstraction layer to the actual transistors to talk about voltages and currents surely?  Actually I wasn't sure if you were talking about the gate terminal on a FET or a logic gate.
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Semantics aside you call it what you will I was referring to it as a gate because thats what that classic structure is was called when I worked for a living and very similar to a CD40106 hex inverter W/O the 'biasing' network for the input function. Gates are made of transistors of all kinds, I would point out that this also meets the classic definition in that the gate can be an input, an output and either high, low or open collector...

Doc
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Quote
Actually I wasn't sure if you were talking about the gate terminal on a FET or a logic gate.
This really shouldn't have been any problem, just look at the 'Subject' of this thread.

Did anyone else notice that the original poster dropped out (with Reply #4) after he got the answer to his question?

Don
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thank you all for the information.
jared
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Quote from:  link=topic=112412.msg845560#msg845560 date=1341174007
At 40 Ma the pin is guaranteed to be at Vcc or ground or close enough that it isn't sensed by the connected load as not quite 1 or 0.

Doc

Where does it say that in the datasheet?
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