I'm content to have learned a little ...
a 0.1uF cap on the voltage divider for fc = 1 / 2(pi)(10,000)(0.1x10-6) = 159 Hz
fc = 1/(2*pi*0.1x10-6*1800) = 883 Hz
... output of the differential amp ... prefer to minimize voltage drop ... I imagine that the current between that op amp and the ADC is minimal ...
... any reason not to shoot for an even lower cutoff/rolloff frequency?
ATmega328 data sheet ... couldn't find anything specifically detailing the input impedance of the ADC.
I don't think this is directly related to the input impedance of the ADC...or is it?
... other basic situations one might commonly encounter where Thevenin's theorem is the tool to use?
I will have to keep my eye out for opportunities to apply the theorem
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