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Author Topic: Unformatted write to SD  (Read 5747 times)
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the quotes are by Walt Kester he is the recognized authority on converters.  His book is the standard reference http://www.amazon.com/Data-Conversion-Handbook-Analog-Devices/dp/0750678410.

Actually the 3LSB offset will reduce ENOB.  The reason is that ENOB is based on how well an ADC digitizes a full scale sine wave.  The 3LSB offset error will distort the wave for low values, returning zero when the voltage is not zero.

That's why ENOB is so useful.  Almost any fault in an ADC will lower ENOB.

So I will stick with people like Walter Kester for information on ADCs, not your guesses.

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That is why I suggested that, since you seem to have got a very clean signal, a suitable cyclic perturbation signal would be better than arbitrary, uncharacterised noise.
You don't listen.  I said I don't do oversampling, I get a better converter.  I never suggested a way to inject noise for oversampling.  I just said oversampling won't work because the noise levels are so low.

I played with resistors and pickup by longer wires between the source and ADC to see how sensitive it was.

Adding a cyclic perturbation signal seems like a really bad idea.  You should just spend $5 for a better ADC.

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This is so basic, I don't see why I am having to lay this out for a third time.
I ignore you because what you are saying is at odds with recognized authorities. 

You don't even know what the definition of resolution is for a ADC.  Show me a link to a definition where the it's other than the number of bits output by the converter.

I have spent my career at the finest science labs in the world.  Some of the world's best analog and mixed signal engineers are in these labs.  As a scientist I depended on them and learned from them.

Who are you?  What is the basis of your authority?   You never answered whether you are really an EE.
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Actually the 3LSB offset will reduce ENOB.  The reason is that ENOB is based on how well an ADC digitizes a full scale sine wave.  The 3LSB offset error will distort the wave for low values, returning zero when the voltage is not zero.

But only if you are sampling within 3 LSB of the extremes of the dynamic range! This is clearly a contrived response that avoids you admitting being wrong on the basic question. Of course that is the reason you avoided it the first time I asked.

If that is your level of argument we are clearly not going to get any further on the technical points so I see no point in further discussion.


I thank you again for contributing the code and the wealth of useful information you were able to provide about SD cards earlier in the thread.


You may wish to review what ATLAS say about whether they have discovered the Higgs Bosson.

http://www.atlas.ch/news/2012/latest-results-from-higgs-search.html

" In the weeks and months ahead, ATLAS will better measure these properties, enabling a clearer picture to emerge about whether this particle is the Higgs Boson, or the first of a larger family of such particles, or something else entirely."


Best wished to you.
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But only if you are sampling within 3 LSB of the extremes of the dynamic range!
I don't think you meant that.  Here is the definition of dynamic range for an ADC:
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Dynamic Range
Typically expressed in dB, dynamic range is defined as the range between the noise floor of a device and its specified maximum output level. An ADC's dynamic range is the range of signal amplitudes which the ADC can resolve; an ADC with a dynamic range of 60dB can resolve signal amplitudes from x to 1000x. Dynamic range is important in communication applications, where signal strengths vary dramatically. If the signal is too large, it over-ranges the ADC input. If the signal is too small, it gets lost in the converter's quantization noise.
I think you meant full scale of the ADC.  Here is the definition of ENOB:
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Effective Number Of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists only of quantization noise. As the input frequency increases, the overall noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD. (See 'Signal-to-Noise and Distortion Ratio (SINAD).') ENOB for a full-scale, sinusoidal input waveform is computed from:

ENOB = (SINAD -1.76)/6.02
Note full-scale.  If you use a smaller signal, you would get the wrong (smaller answer).

Want to bet on Higgs?   I may be wrong, not all properties have been verified.  On the other hand not all group information is public so you might want to think before you bet.  The correct decays have been seen but now the equivalent of oversampling is happening to be totally sure.  Hope you read the latest paper that has just been submitted to "Physics Letters B" when it's published. 

You need to lighten up a bit and so do I.  Here's how http://www.wikihow.com/Lighten-Up.  This is a summary:
Quote
1. Stop assuming you know everything. Nobody knows everything.

2. Stop exaggerating. Exaggerating about your abilities, qualifications, knowledge, hobbies etc. is soon tiresome.

3. Let go of things. It's OK to lose an argument; it's OK to make mistakes.

4. Laugh.

5. Delegate.

6. Stop being so rules focused.

You're welcome for the code and any information you can use.  I will try to lighten up also.
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You need to lighten up a bit and so do I.  Here's how http://www.wikihow.com/Lighten-Up.  This is a summary:

Good idea, nice summary.

I'll keep an eye for news on Higgs. I'm sure all public statements are being rigorously cautious. We don't want another round like the super-neutrinos smiley-wink

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Finally got my SD hardware from Holland, took 13 days for the post !!

So now I can start some real work.

I also found out that the standard analogRead is fairly inefficient with 16b reads:

http://arduino.cc/forum/index.php/topic,120419.msg908130.html#msg908130

It also has what seems like a spurious 1000us delay !
Code:
// ### WTF???
// without a delay, we seem to read from the wrong channel
// delay(1);
...

// low  = ADCL;
// high = ADCH;
// return (high << 8) | low;
//        return (ADCL | ADCH<<8);
        return ADC;  // shrinks 8ops to 3 ops !  compiler does correct read order

Added similar mod to your test code AnalogIsrLogger:
Code:
#if RECORD_EIGHT_BITS
  uint8_t d = ADCH;
#else  // RECORD_EIGHT_BITS
//  uint8_t low = ADCL;
//  uint8_t high = ADCH;
//  uint16_t d = (high << 8) | low;
  uint16_t d = ADC;
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Thanks, I meant to check if the compile order was correct for 16-bit access but never got back to it.  
« Last Edit: August 30, 2012, 10:15:08 am by fat16lib » Logged

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The strange 1 ms delay was removed a long time ago. 

I did a check on 1.0.1 running this sketch and it performs as expected for a 125 kHz ADC clock.

Code:
void setup() {
  Serial.begin(9600);
  uint32_t t0 = micros();
  uint16_t v0 = analogRead(0);
  uint32_t t1 = micros();
  uint16_t v1 = analogRead(0);
  uint32_t t2 = micros();
  Serial.println(t1 - t0);
  Serial.println(t2 - t1);
}
void loop() {}
It prints
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212
112

The first call takes 26.5 ADC clock cycles, a bit more than 25 required by the hardware.

The second takes 14 ADC clock cycles, again a bit longer than the time required by the hardware.

I did some more ADC tests that you might look at http://arduino.cc/forum/index.php/topic,120004.0.html.

These tests show how important calibration is and examine Noise Reduction Mode.
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The strange 1 ms delay was removed a long time ago. 

Curious. I only got into Arduino a few weeks back and downloaded the 1.0.1 software directly (not a distro package because my distro did not have 1.0.1) and the lines I posted were present in that bundle.

Non modified files are dated 22nd May 2012.

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I have set up a PWM on pin3 using timer2 but found that even a nominally "empty" ISR on that clock broke Serial.print() pretty fast, though sometimes it did get one or two chars across. The link was lost and USB device disappeared on linux host.

That connection is expendable but I anticipate similar issues with SD.

I need to control external hardware that probably needs some simple maths and an adjustment to the PWM duty cycle something like 20 - 100 times per second.

What would be required to have another ISR running without breaking SDlib ?  Is that possible ?

Thanks for any pointers you can give.

BTW, I've estimated the maths and one port write  ISR < 4us
« Last Edit: September 08, 2012, 06:02:58 am by ardnut » Logged

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