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Dubai, UAE
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How to view assembly

http://rcarduino.blogspot.com/2012/09/how-to-view-arduino-assembly.html

Duane B

rcarduino.blogspot.com
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The limit of 30 for OCR2A-OCR2B is probably due to the time for ISR call, the storing and retrieving of registers, ect.

Yes, it is due to interrupt latency: when the 1st interrupt is being serviced (the context saving takes around 20 ticks), global interrupt is disabled. But if the 2nd interrupt arrives before the exeution of the 1st isr is finished, it is not serviced until the 1st interrupt is finished and global interrupt is re-enabled.

gcc-avr, the compiler behind the arduino ide, is actually quite good. You may speed up using more optimization (-O3 for example), or naked isr (no automatic context saving).

Using isr allows you to get very accurate timing. You just need to know its limitations.
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I played with it a little in gcc-avr. With naked isr, the lowest I can get between the two isrs is about 10 ticks -> <1us @ 16MIPS.
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The risk with naked isrs is that you have to look at the generated assembly and perform context save (push/pop) yourself.
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I repeat that to get jitter-free timer output you have to use the hardware timer output. Not an ISR.
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http://www.gammon.com.au/electronics

Please post technical questions on the forum - not to me by personal message. Thanks a lot.

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to get jitter-free timer output

There is no jitter-free output of any kind. Phase noise is a fact of life in oscillators. They all exhibit certain degrees of jitter.

The more important question is: can your application live with such imperfection? or can you design around it? or can you compromise? A jittery but otherwise accurate oscillator for example is far better than a jitter-free but inaccurate oscillator for a clock.
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Pisa - Italy
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I repeat that to get jitter-free timer output you have to use the hardware timer output. Not an ISR.
to use the hardware timer output is surely a good idea by many point of view, unfortunately in my case, as I wrote in my post, I have to update a DAC and this require in sequence to put two bytes on a buffer, to set a write bit and to set a load bit, impossible to do with just a timer output and easy to do with ISR. If you have MIPS enough.
Next time I'll define the subject of my post "DAC update"  in place of "timer programming".
Thanks to all of you and expecially to dhenry for all the tests and naked isr.
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Pisa - Italy
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Thanks, really useful link!
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... hardware timer output is surely a good idea ...[but] I have to update a DAC ...
I've gotten good results getting an audio-frequency signal from a DAC using a hardware timer.  Most DAC's have a "load" input, often called "LDAC," usually active low, that transfers data from internal holding registers to the DAC output register, so that multiple DACs can be loaded in sequence, and update their outputs simultaneously.  The hardware timer fires the LDAC pulse; the next data sample is loaded into the DAC by an ISR, or in the main program.

The timer is set up like this:
  • Waveform Generation Mode = Fast PWM
  • Compare Output Mode A = Normal, OCXA disconnected
  • Compare Output Mode B = OCXB set on match/clear at BOTTOM, or opposite, depending on the requirements of the DAC
  • Clock Select and OCRXA as required to generate the required DAC update frequency
  • OCRXB to provide a pulse of appropriate length to the DAC
  • Interrupt on OCRXB compare match enabled; other interrupts disabled

OCXB is connected to LDAC.  The first sample is loaded to the DAC's internal registers in setup(), then the timer is started.  ISR(TIMERX_COMPB_vect) loads the next sample into the DAC's internal registers, bumps the pointer, and exits.  When the timer rolls over, the output goes low, and the data is loaded into the DAC's output registers, without any action from the program.  If the timing isn't too fast, the ISR could instead signal the main program, and let the main handle the I/O.

For something like frequency synthesis, where timing accuracy matters, this method is superior to updating the DAC output from inside an ISR.  There's no problem with interrupt latency, and no chance that the timer will fire late because some other interrupt was being serviced at the time.  It may not be theoretically "jitter-free," but its jitter is so much reduced that, from a practical standpoint, you could call it "jitter-free."
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Thats interesting, i have been using ISRs to generate DDS Audio and hadnt even considered the impact of the other ISRs on the sound quality, anyway its nice to know that there is a neat solution in your suggestion.

Thanks

Duane B

rcarduino.blogspot.com
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Pisa - Italy
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...
For something like frequency synthesis, where timing accuracy matters, this method is superior to updating the DAC output from inside an ISR.  There's no problem with interrupt latency, and no chance that the timer will fire late because some other interrupt was being serviced at the time.  ..."

Thanks, very nice idea!
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