To me it seems that you want to make some kind of two-headded Frankenstein-Arduino. It is not Halloween, and too early for Aprils-fool-day.
The data acquisition is done with system A that receives the data at the rate of "0.1 upto 2 second". The system B needs up to 30 second to deal with every data presented to him by system A. So every time you lose almost 20 data because the system B is too slow. So if I had a memory, I would place some data coming from system A there while trying to improve the capacity of system B.
....A big problem is that the small AVRs just don't have an "external memory interface." Reading or writing to an I2C memory is relatively slow, and may add more complexity than it's worth.
Both sides need something like HC125 to buffer the CS, SCK, and MOSI outputs and not drive them when not active. CS can be used to enable the OE pins. And still need a line that both sides can monitor to see if the part is free.
19.3.2 Master ModeWhen the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SSpin.If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically,the pin will be driving the SS pin of the SPI Slave.If SS is configured as an input, it must be held high to ensure Master SPI operation. >>>>>>If the SS pin is driven low byperipheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI systeminterprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid buscontention, the SPI system takes the following actions:1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave,the MOSI and SCK pins become inputs.2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interruptroutine will be executed.Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS isdriven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared bya slave select, it must be set by the user to re-enable SPI Master mode.
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