Bit 4 - ACI: Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Una domandina: perché, a livello di programmazione lavorando direttamente con i registri dell'ATmega, per resettare un flag di interrupt ci devo scrivere 1 anziché 0?
Ma relativamente agli Atmega? O in generale?
Mi sembrava di ricordarmi che il professore ci disse che c'era un motivo perché viene fatto così,
There are basically two types of interrupts. The first type is triggered by an event that sets theInterrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vectorin order to execute the interrupt handling routine, and hardware clears the correspondingInterrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit iscleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag iscleared by software. Similarly, if one or more interrupt conditions occur while the Global InterruptEnable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until theGlobal Interrupt Enable bit is set, and will then be executed by order of priority.
Mi sa che stai facendo un po' di confusione con la traduzione Lì si para del comportamento inerente la gestione degli interrupt ma non dice che "set" equivale a 1. Normalmente, a meno che non sia diversamente specificato (vedi fuse), "set" vuol dire messo ad 1.
....Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared....
Bit 1 - INTF1: External Interrupt Flag 1When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.Alternatively, the flag can be cleared by writing a logical one to it. This flag is always clearedwhen INT1 is configured as a level interrupt.• Bit 0 - INTF0: External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.Alternatively, the flag can be cleared by writing a logical one to it. This flag is always clearedwhen INT0 is configured as a level interrupt.
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