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Topic: New SdFat optimized for Mega and Teensy 3.0 (Read 7 times) previous topic - next topic

fat16lib

pito,

I was able to try 16-bit frames.  The write rate increased from 1776.44 KB/sec to 2013.34 KB/sec.

The overhead is increased since a byte swap is required.  I form the 16-bit word to be sent like this:

Code: [Select]

    uint16_t w = *src++ << 8;
    w |= *src++;

pito

..the ref manual says it can do 32bit transfers as well.. :)

fat16lib

#7
Oct 23, 2012, 01:20 pm Last Edit: Oct 23, 2012, 01:29 pm by fat16lib Reason: 1
The RX FIFO appears to be 32-bits wide but:
Quote

3.9.2.5 RX FIFO Size
SPI supports up to 16-bit frame size during reception.

The TX FIFO is 32-bits wide but the high 16-bits are command bits.
Quote

43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO . 8- or 16-bit write accesses to the Data Field of PUSHR
transfers the 16 bit Data field of PUSHR to the TX FIFO. Write accesses to the
Command Field of PUSHR transfers the 16 bit Command Field of PUSHR to the TX
FIFO. The register structure is different in Master and Slave modes. In Master mode, the
register provides 16-bit command and data to the TX FIFO. In Slave mode, the 16 bit
Command Field of PUSHR is reserved.


Even if you could send 32 bits, the byte order in memory is not in the correct order due to nature of a little-endian fetch from memory to a 32 bit register.

See above for the problem with 16-bit transfers.

The datasheet is not too clear in spots.  See point 8 in this list:
Quote

TOP TEN THINGS ENGINEERING SCHOOL DIDN'T TEACH YOU (from Rich Ries via Embedded Muse)
10. There are at least 10 types of capacitors.
9. Theory tells you how a circuit works, not why it does not work.
8. Not everything works according to the specs in the databook.
7. Anything practical you learn will be obsolete before you use it,
except the complex math, which you will never use.
6. Always try to fix the hardware with software.
5. Engineering is like having an 8 a.m. class and a late afternoon lab
every day for the rest of your life.
4. Overtime pay? What overtime pay?
3. Managers, not engineers, rule the world.
2. If you like junk food, caffeine and all-nighters, go into software.
1. Dilbert is not a comic strip, it's a documentary.

pito

:~
Figure 43-1. DSPI Block Diagram  - shows 32bit data path to the shift register (and and extra for command)
43.1.2 "SPI frames longer than 16 bits can be supported using the continuous selection format"..
43.3.9 "Eight- or sixteen-bit read accesses to the POPR have the same effect on the RX FIFO as 32-bit read accesses"..
43.4.2 "The SPI frames can be 32 bits long."..

3. Sales Managers, not engineers, rule the world.
:)

fat16lib

Yes you can read SPIx_POPR as a 32 bit register but only 16 bits are data.  See 3.9.2.5
Quote

Figure 43-1. DSPI Block Diagram  - shows 32bit data path to the shift register (and and extra for command)

Figure 43-1 is wrong.  See rule 8 in my previous post.  See  43.3.7 for the format of PUSHR.
Quote

43.1.2 "SPI frames longer than 16 bits can be supported using the continuous selection format"..

Continuous selection format just insures that CS remains low, it has nothing to do with the FIFOs.
Quote

CONT
Continuous Peripheral Chip Select Enable
Selects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selected
PCS signals to remain asserted between transfers.
0 Return PCSn signals to their inactive state between transfers.
1 Keep PCSn signals asserted between transfers.


Quote

43.4.2 "The SPI frames can be 32 bits long."..


Frames can be any size but a max of 16 bits can be transferred to/from the FIFOs.  Unfortunately the data sheet uses Frame size for two things.

In the CTAR 43.3.3 it is how many bits wide the data field is in a FIFO.

In other places it is how many bits are sent in a transfer while CS is low.

Again the datasheet is a clue for Kinetis and point 8 above applies to many sections.

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