uint16_t w = *src++ << 8; w |= *src++;
22.214.171.124 RX FIFO SizeSPI supports up to 16-bit frame size during reception.
43.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)PUSHR provides the means to write to the TX FIFO. Data written to this register istransferred to the TX FIFO . 8- or 16-bit write accesses to the Data Field of PUSHRtransfers the 16 bit Data field of PUSHR to the TX FIFO. Write accesses to theCommand Field of PUSHR transfers the 16 bit Command Field of PUSHR to the TXFIFO. The register structure is different in Master and Slave modes. In Master mode, theregister provides 16-bit command and data to the TX FIFO. In Slave mode, the 16 bitCommand Field of PUSHR is reserved.
TOP TEN THINGS ENGINEERING SCHOOL DIDN'T TEACH YOU (from Rich Ries via Embedded Muse)10. There are at least 10 types of capacitors.9. Theory tells you how a circuit works, not why it does not work.8. Not everything works according to the specs in the databook.7. Anything practical you learn will be obsolete before you use it,except the complex math, which you will never use.6. Always try to fix the hardware with software.5. Engineering is like having an 8 a.m. class and a late afternoon labevery day for the rest of your life.4. Overtime pay? What overtime pay?3. Managers, not engineers, rule the world.2. If you like junk food, caffeine and all-nighters, go into software.1. Dilbert is not a comic strip, it's a documentary.
Figure 43-1. DSPI Block Diagram - shows 32bit data path to the shift register (and and extra for command)
43.1.2 "SPI frames longer than 16 bits can be supported using the continuous selection format"..
CONTContinuous Peripheral Chip Select EnableSelects a continuous selection format. The bit is used in SPI Master mode. The bit enables the selectedPCS signals to remain asserted between transfers.0 Return PCSn signals to their inactive state between transfers.1 Keep PCSn signals asserted between transfers.
43.4.2 "The SPI frames can be 32 bits long."..