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Author Topic: Testing a 74LS181  (Read 910 times)
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Brattain Member
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That, I would say, is a sign of some serious problem somewhere else.
And I would not.
It chimes in with my experience of using TTL over the last 40 or so years.
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I also thought that the value was lower than usual.

If you post a schematic, I am sure we can help you find out what's wrong.
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I also thought that the value was lower than usual. But it seems to coincide with what Grumpy_Mike said. The datasheet, however, says 1.2mA is enough to pull it low.

No, the worst case inputs (S inputs) require -1.6mA when low.  Thus to bring below 0.8V you need less than 500 ohm pull downs, to bring down to 0.4V suggests less than 250 ohms (you do want noise immunity!).
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Ok, I drew up and attached a schematic. I've also noticed that if all of the A and B inputs are pulled low my current draw is ~150mA and when they're high it gets up to ~300mA!


* 74ls181.bmp (1819.65 KB, 1065x583 - viewed 17 times.)
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TTL logic of the 70's was very power hungry... it is probably the best explanation for why CMOS logic was accepted with open arms by many designers and it ended up being used wherever it made sense.
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Ok, I drew up and attached a schematic. I've also noticed that if all of the A and B inputs are pulled low my current draw is ~150mA and when they're high it gets up to ~300mA!

The pull downs are clearly responsible for the difference between those two figures (why have pull downs at all?  This is an odd way to use TTL)

The large value of the supply current makes me think ether the chip is broken or its a 74S181 rather than a 74LS181...
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