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[Reply #15 on:]

Run the RC signal thru a buffer so that it puts out a nice clean edge.
A simple op-amp/comparator would do it - output stays at low level until the cap charges up to the comparison level, and then the output flips, nice & clean.
Logic devices with "schmitt trigger" inputs are designed to do that. Here is an example device
http://www.ti.com/lit/ds/symlink/sn74lvc1g17.pdf

[Reply #16 on:]

Run the RC signal thru a buffer so that it puts out a nice clean edge.
A simple op-amp/comparator would do it - output stays at low level until the cap charges up to the comparison level, and then the output flips, nice & clean.
Logic devices with "schmitt trigger" inputs are designed to do that. Here is an example device
http://www.ti.com/lit/ds/symlink/sn74lvc1g17.pdf

This register has inside trigger with hysteresis, why should I add extra external trigger?

[Reply #17 on:]

You are inferring that from something in the data sheet? I see no mention of hysterisis.
Nor a minimum rise time on the clock signals, only that the testing was done with <=10nS rise & fall times.
So maybe it doesn't matter, as long as the current into the cap is limited to not overstress the pin driving the serial clock line.
http://www.ti.com/lit/ds/symlink/tpic6a595.pdf

[Reply #18 on:]

page 5
High-level input voltage, VIH 0.85 VCC VCC V
Low-level input voltage, VIL 0 0.15 VCC V
Also there is EQUIVALENT OF EACH INPUT, on page 4.


About max frequency, same page
Pulse duration, tw (see Figure 2) 20 ns

but I'm talking about frequency due to cable limitations, not register limitations.