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[on:]

Just got my Due and would like to implement a mono audio delay circuit as a test project/challenge.

I will use the onboard 12bit ADC and DAC so the only peripherals I will need (other than condition audio i/o for the correct voltage levels) is RAM for the delay buffer.  I would like to get delay times in the range of a few seconds.

So what should I use for the memory bank and how would I ideally interface this to the Due platform? 

[Reply #1 on:]

What datarate are you sampling at?
CD quality audio is sampled at 44.1K samples/second.
You could probably get by with 32K samples at 12Bit sampling.
For "a few seconds" you will need "a few" banks of 32k x 8 SRAMs with 2 SRAMs in each bank.
That will support an audio frequency range of ~15KHz.
You'll have to do the math and see if you  can use Serial interface RAM (SPI), or parallel.
Parallel would need 15 address lines, 12 data lines, WE/,OE/ to all chips and a CE/ to each bank.
If coding supports direct port manipulation, then you might have something like:
sample time?{
read adc
write high address port with output address
write low address port with output address
write data port
write control line port for CEx low
write control line port for CEx high
update output address count & CEx if needed

write high address port with input address
write low address port with input address
write control line port for CEx low
read data port
write control line port for CEx high
write DAC
update input address count & CEx if needed

}

the delta in address range between the write address and the read address (which must be lower than the write address) will determine the delay.

You'll have to take care to wrap the address counter back around to 0 after reaching the last address of the last bank and to ensure that the read address always follows the write address.

[Reply #2 on:]

I think I would try with parallel interface ram just to ensure best performance. I would like to see if I could double the sample rate (obviously cuts down the max time of the delay).

Are there any specific chips you would recommend I use or is there a shield that exists that could be modified for this purpose?
What about this QuadRAM shield from Rugged http://ruggedcircuits.com/html/quadram.html

Also once this system is working I will try using a dedicated audio codec using the I2S interface.

[Reply #3 on:]

"I think I would try with parallel interface ram just to ensure best performance. "
 but then you'll cripple performance with
"I will try using a dedicated audio codec using the I2S interface." with its 400Kbit/sec max serial transfer speed.
why? If anything go with something that has SPI interface for 4 Mbit/sec serial transfer speed.

Yes, the quad ram would work nice. I had forgotten about that.

I was thinking something like banks of these
http://www.mouser.com/ProductDetail/Alliance-Memory/AS6C1008-55PCN/?qs=sGAEpiMZZMt9mBA6nIyysPeGHDtAZQ%252bH2gVKyfvad7s%3d
for a thru hole part. Its on the big side physically, but not surface mount so its easy to prototype with. 

[Reply #4 on:]

Do NOT connect a QuadRAM to a Due, at least not before consulting the designer to ask if it is safe. From reading the schematic I believe the Quadram may be working at 5v and could damage the Due.

[Reply #5 on:]

QuadRAM Shield for Arduino Mega/Mega2560

schematic shows its a 5V part. Also, the Mega2560 has memory expansion pins while, unless I am mistaken, the Due does not.

[Reply #6 on:]

Hmm, yes, the quadram needs 5v to work, so maybe not a good option. Underpowering it won't damage anything, it just won't work.

However, 3.3V versions of the chip are also available
http://www.mouser.com/ProductDetail/Alliance-Memory/AS7C34096A-12TIN/?qs=sGAEpiMZZMt9mBA6nIyysDfDw0vDQxSwaJg9Cfc3Tkc%3d
so the Rugged Circuits folks could change the address latch to a 3.3V part and have a Due compatible board.
Whether the part fits neatly into the Due address space is different matter. If the sketch is directly controlling the memory addressing as I outlined above, I don't think it matters.

[Reply #7 on:]

" with its 400Kbit/sec max serial transfer speed.
why? If anything go with something that has SPI interface for 4 Mbit/sec serial transfer speed.

I am talking about I2S not I2C. AFAIK I2S will give Mbit transfer speeds and it is perfectly suited for data rates of stereo cd quality audio.

[Reply #8 on:]

Hmm, yes, the quadram needs 5v to work, so maybe not a good option. Underpowering it won't damage anything, it just won't work.

However, 3.3V versions of the chip are also available
http://www.mouser.com/ProductDetail/Alliance-Memory/AS7C34096A-12TIN/?qs=sGAEpiMZZMt9mBA6nIyysDfDw0vDQxSwaJg9Cfc3Tkc%3d
so the Rugged Circuits folks could change the address latch to a 3.3V part and have a Due compatible board.
Whether the part fits neatly into the Due address space is different matter. If the sketch is directly controlling the memory addressing as I outlined above, I don't think it matters.

I am comfortable working with SMD ICs  (lot's of experiencing desoldering them too) so I may try getting the shield and replacing latch IC  and memory with 3.3V part.

[Reply #9 on:]

but then you'll cripple performance with
"I will try using a dedicated audio codec using the I2S interface." with its 400Kbit/sec max serial transfer speed.
why?

Because I2S is specifically designed for handling high-speed digital audio, such as between a CD transport and an outboard DAC.

Your estimate of the bandwidth is way off, I2S uses clock rates around 2 to 12MHz (depending on sample rate, word length and number of channels). It can cope with 24/192 so is entirely capable of 12/30.

[Reply #10 on:]

Ok, looking at the I2S spec:

"As shown in Figure 1, the bus has three lines:
• continuous serial clock (SCK);
• word select (WS);
• serial data (SD);
and the device generating SCK and WS is the master."
that looks more like SPI to me with the slave select line not really used, a left/right line being used instead.