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Topic: ADC0 and the ATTiny85 (Read 1 time) previous topic - next topic

Papa G

This may be common knowledge but I wasn't able to find anything about it while searching the forum, so I thought I'd mention it.

I was testing my first ATTiny application, a thermostat to replace the broken one in an RV propane/electric refrigerator/freezer, and found an interesting bug. My application uses ADC0, ADC2, ADC3, and three digital I/O pins for communication and SSR control. The ATTiny only has 8 pins so I am using everything it's got. ADC0 shares pin 1 with /Reset and some other functions.

I know what my temperature normally runs so I was testing the accuracy of each channel by placing the thermistor under my tongue. While doing this with ADC0, i noticed that every time the temperature reached around 85 degrees F, the processor would restart. It took me a few minutes to realize that this was at the Vrst threshold and that unless external reset is disabled by programming bit 7 in the fuse high byte, it is active no matter what you are using the pin for.

So, if you are not using the /reset pin for external reset, remember to program the proper fuse bit or your application may not work as planned. Also, unless you have a high voltage programmer, don't program the fuse bit until you are through programming the flash because programming hfuse bit 7 disables normal flash programming.

This just happened to be the ADC channel I picked for external temperature so if I had used it for refrigerator internal temperature I would likely have never run into a problem.

Papa G

I got a high voltage programmer so I decided it was time to see what effect programming the RSTDISBL fuse bit would have. I need to preface this experiment with the fact that ADC0 results were consistently about 10 LSBs high compared to other ADC channels. Programming RSTDISBL brought ADC0 back into spec as well as preventing a voltage <= Vrst from resetting the chip.

fungus


ADC0 results were consistently about 10 LSBs high compared to other ADC channels. Programming RSTDISBL brought ADC0 back into spec as well as preventing a voltage <= Vrst from resetting the chip.


The reset pin has an internal pullup resistor on it. That was probably causing the offset.
No, I don't answer questions sent in private messages (but I do accept thank-you notes...)

Papa G

I didn't think about that. That would explain it. The reset pin must enable its pull-up if not specifically disabled because all the PortB pins have pull-ups.

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